公开(公告)号：US11004734B2

公开(公告)日：2021-05-11

申请号：US16672879

申请日：2019-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Yu-Kai Lin ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311

Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.

公开(公告)号：US20210134656A1

公开(公告)日：2021-05-06

申请号：US17119692

申请日：2020-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ren Wang ,  Shing-Chyang Pan ,  Ching-Yu Chang ,  Wan-Lin Tsai ,  Jung-Hau Shiu ,  Tze-Liang Lee

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

公开(公告)号：US10685873B2

公开(公告)日：2020-06-16

申请号：US15197294

申请日：2016-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/485

Abstract: A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

公开(公告)号：US10535816B2

公开(公告)日：2020-01-14

申请号：US16059777

申请日：2018-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A via structure, a MRAM device using the via structure and a method for fabricating the MRAM device are provided. In the method for fabricating the MRAM device, at first, a first dielectric layer is deposited over a transistor. Then, a contact is formed in the first dielectric layer and electrically connected to the transistor. Thereafter, a metal nitride layer is deposited over the first dielectric layer and the contact. Then, an etch stop layer is deposited over the metal nitride layer. Thereafter, a second dielectric layer is deposited over the etch stop layer. Then, a via structure is formed in the second dielectric layer, the etch stop layer, and the metal nitride layer and landing on the contact. Thereafter, a memory stack is formed over the via structure.

公开(公告)号：US10522360B2

公开(公告)日：2019-12-31

申请号：US15730934

申请日：2017-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Ling Lee ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Wen-Cheng Yang ,  Chih-Tsung Lee ,  Victor Y. Lu

IPC: H01L21/285 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber. The method also includes introducing a plasma-forming gas into the PVD chamber, and the plasma-forming gas contains an oxygen-containing gas. The method further includes applying a radio frequency (RF) power to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. In addition, the method includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.

公开(公告)号：US20190333807A1

公开(公告)日：2019-10-31

申请号：US15964306

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Yu-Kai Lin ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311

Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.

公开(公告)号：US09567668B2

公开(公告)日：2017-02-14

申请号：US14183670

申请日：2014-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Chi ,  Shing-Chyang Pan ,  Kuan-Chia Chen ,  Yao-Jen Chang ,  Huang-Yi Huang ,  Ching-Hua Hsieh

IPC: C23C14/34 ,  C23C14/35 ,  H01J37/34 ,  C23C14/54

CPC classification number: C23C14/35 ,  C23C14/3492 ,  C23C14/542 ,  H01J37/3405 ,  H01J37/3452 ,  H01J37/3455 ,  H01J37/3458

Abstract: Embodiments of a plasma apparatus are provided. The plasma apparatus includes a processing chamber and a wafer chuck disposed in the processing chamber. The plasma apparatus also includes a target element located over the wafer chuck and an electromagnet array located over the target element and having a number of electromagnets. Some of the electromagnets in a magnetic-field zone of the electromagnet array are enabled to generate a magnetic field adjacent to the target element. The magnetic-field zone is moved during a semiconductor manufacturing process.

Abstract translation: 提供了等离子体装置的实施例。 等离子体装置包括设置在处理室中的处理室和晶片卡盘。 等离子体装置还包括位于晶片卡盘上方的目标元件和位于目标元件上方并具有多个电磁体的电磁体阵列。 电磁体阵列的磁场区域中的一些电磁体能够产生与目标元件相邻的磁场。 磁场区在半导体制造过程中移动。

公开(公告)号：US09385086B2

公开(公告)日：2016-07-05

申请号：US14102090

申请日：2013-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Hong-Hui Hsu

IPC: H01L23/48 ,  H01L21/4763 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76879 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A robust metallization profile is formed by forming two or more layers of hard mask with different density. Multi-layer metal hard mask is helpful especially in small feature size process, for example, 50 nm and below. Lower layers have higher density. In such ways, enough process window is offered by lower layers and at the same time, round hard mask profile is offered by upper layers.

Abstract translation: 通过形成具有不同密度的两层或更多层硬掩模形成坚固的金属化轮廓。 多层金属硬掩模有助于特别是在小特征尺寸过程中，例如50nm及以下。 较低的层具有较高的密度。 以这种方式，较低层提供了足够的工艺窗口，同时由上层提供圆形硬掩模。

公开(公告)号：US20210280460A1

公开(公告)日：2021-09-09

申请号：US17316063

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Ping Tung ,  Yu-Kai Lin ,  Jen Hung Wang ,  Shing-Chyang Pan

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/311

Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.

公开(公告)号：US20210024348A1

公开(公告)日：2021-01-28

申请号：US16521907

申请日：2019-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Sung Chang ,  Chun-Wen Cheng ,  Fei-Lung Lai ,  Shing-Chyang Pan ,  Yuan-Chih Hsieh ,  Yi-Ren Wang

IPC: B81B3/00 ,  B81C1/00

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.