公开(公告)号：US20240136222A1

公开(公告)日：2024-04-25

申请号：US18543934

申请日：2023-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi TSAI ,  Tsung-Lin LEE ,  Yen-Ming CHEN

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76832 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).

公开(公告)号：US20240097033A1

公开(公告)日：2024-03-21

申请号：US18521584

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Jen LAI ,  Yen-Ming CHEN ,  Tsung-Lin LEE

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/4966

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

公开(公告)号：US20200161335A1

公开(公告)日：2020-05-21

申请号：US16665791

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung CHEN ,  Tsung-Lin LEE ,  Chung-Ming LIN ,  Wen-Chih CHIANG ,  Cheng-Hung WANG

IPC: H01L27/12 ,  H01L23/535 ,  H01L21/74

Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

公开(公告)号：US20190341473A1

公开(公告)日：2019-11-07

申请号：US16511719

申请日：2019-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng YUAN ,  Hung-Ming CHEN ,  Tsung-Lin LEE ,  Chang-Yun CHANG ,  Clement Hsingjen WANN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/308

Abstract: The fin structure includes a first portion and a second, lower portion separated at a transition. The first portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.

公开(公告)号：US20190136373A1

公开(公告)日：2019-05-09

申请号：US16021448

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung YEH ,  Tsung-Lin LEE ,  Yi-Ming LIN ,  Sheng-Chun YANG ,  Tung-Ching TSENG

IPC: C23C16/44 ,  C23C16/52 ,  H01J37/32 ,  C23C16/455

Abstract: A chemical vapor deposition (CVD) apparatus is provided. The CVD apparatus includes a CVD chamber including multiple wall portions. A pedestal is disposed inside the CVD chamber, configured to support a substrate. A gas inlet port is disposed on one of the wall portions and below a substrate support portion of the pedestal. In addition, a gas flow guiding member is disposed inside the CVD chamber, coupled to the gas inlet port, and configured to dispense cleaning gases from the gas inlet port into the CVD chamber.

公开(公告)号：US20180337176A1

公开(公告)日：2018-11-22

申请号：US16049059

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying LEE ,  Meng-Hsuan HSIAO ,  Tsung-Lin LEE ,  Chih Chieh YEH ,  Yee-Chia YEO

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/66545

Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US20240371881A1

公开(公告)日：2024-11-07

申请号：US18769227

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung CHEN ,  Tsung-Lin LEE ,  Chung-Ming LIN ,  Wen-Chih CHIANG ,  Cheng-Hung WANG

IPC: H01L27/12 ,  H01L21/74 ,  H01L23/535

Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

公开(公告)号：US20240363495A1

公开(公告)日：2024-10-31

申请号：US18767848

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung CHEN ,  Cheng-Hung WANG ,  Tsung-Lin LEE ,  Shiuan-Jeng LIN ,  Chun-Ming LIN ,  Wen-Chih CHIANG

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/58 ,  H01L29/06

CPC classification number: H01L23/481 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31116 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/585 ,  H01L29/0649

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US20220367523A1

公开(公告)日：2022-11-17

申请号：US17876409

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung CHEN ,  Tsung-Lin LEE ,  Chung-Ming LIN ,  Wen-Chih CHIANG ,  Cheng-Hung WANG

IPC: H01L27/12 ,  H01L21/74 ,  H01L23/535

Abstract: Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.

公开(公告)号：US20200144126A1

公开(公告)日：2020-05-07

申请号：US16730320

申请日：2019-12-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzung-Yi TSAI ,  Yen-Ming CHEN ,  Tsung-Lin LEE ,  Chih-Chieh YEH

IPC: H01L21/8234 ,  H01L27/088

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.