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    Rotary EUV collector
    12.
    发明授权
    Rotary EUV collector 有权
    旋转EUV收集器

    公开(公告)号：US09429858B2

    公开(公告)日：2016-08-30

    申请号：US14035268

    申请日：2013-09-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shang-Chieh Chien ,  Shu-Hao Chang ,  Jui-Ching Wu ,  Tsung-Yu Chen ,  Tzu-Hsiang Chen ,  Ming-Chin Chien ,  Chia-Chen Chen ,  Jeng-Horng Chen

    IPC: G03F7/20

    CPC classification number: G03F7/7015 ,  G02B5/0891 ,  G02B7/1821 ,  G03F7/2008 ,  G03F7/2037 ,  G03F7/70033 ,  G03F7/70175 ,  G03F7/70916 ,  G03F7/70925 ,  G21K1/067

    Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.

    Abstract translation: EUV收集器在EUV光刻系统的操作期间或之间旋转。 旋转EUV收集器导致污染物更均匀地分布在收集器的表面上。 这降低了EUV光刻系统随着污染增加而失去图像保真度并从而增加了集电器寿命的速率。 在EUV光刻系统运行期间旋转收集器可以引起对流并降低污染率。 通过以足够的速度旋转收集器，可以通过离心力的作用去除一些污染的碎屑。

    Package structure
    15.
    发明授权
    Package structure 有权

    公开(公告)号：US11282825B2

    公开(公告)日：2022-03-22

    申请号：US16877504

    申请日：2020-05-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

    IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/40 ,  H01L23/46

    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

    PACKAGE STRUCTURE
    16.
    发明申请
    PACKAGE STRUCTURE 有权

    公开(公告)号：US20210366889A1

    公开(公告)日：2021-11-25

    申请号：US16877504

    申请日：2020-05-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

    IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/46 ,  H01L23/40

    Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

    Heat Spreading Device and Method
    17.
    发明申请
    Heat Spreading Device and Method 有权

    公开(公告)号：US20210280491A1

    公开(公告)日：2021-09-09

    申请号：US17328266

    申请日：2021-05-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsung-Shu Lin ,  Wensen Hung ,  Hung-Chi Li ,  Tsung-Yu Chen

    IPC: H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

    Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

    Chip package structure
    18.
    发明授权
    Chip package structure 有权

    公开(公告)号：US10790254B2

    公开(公告)日：2020-09-29

    申请号：US16277806

    申请日：2019-02-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Yu Huang ,  Sung-Hui Huang ,  Shu-Chia Hsu ,  Leu-Jen Chen ,  Yi-Wei Liu ,  Shang-Yun Hou ,  Jui-Hsieh Lai ,  Tsung-Yu Chen ,  Chien-Yuan Huang ,  Yu-Wei Chen

    IPC: H01L29/40 ,  H01L21/44 ,  H01L23/00 ,  H01L21/56 ,  H01L23/522

    Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.

    Semiconductor Device and Methods of Manufacture
    19.
    发明申请
    Semiconductor Device and Methods of Manufacture 有权

    公开(公告)号：US20250022763A1

    公开(公告)日：2025-01-16

    申请号：US18352363

    申请日：2023-07-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Han Tsai ,  Tsung-Yu Chen ,  Hong-Yu Guo ,  Tsung-Shu Lin

    IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29 ,  H01L25/10

    Abstract: Semiconductor device and methods of manufacture are provided. In an embodiment, the a semiconductor device may include a first semiconductor die; an oxide layer on the first semiconductor die, wherein the first semiconductor die has a first top surface opposite the oxide layer; a first insulating material encapsulating the first semiconductor die and the oxide layer, wherein the first insulating material has a second top surface planar with the first top surface; and a first polymer buffer disposed between a sidewall of the first semiconductor die and a sidewall of the oxide layer, wherein the first polymer buffer has a third top surface planar with both the first top surface and the second top surface.

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