公开(公告)号：US20210098452A1

公开(公告)日：2021-04-01

申请号：US17121495

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L27/02 ,  H01L29/78

Abstract: Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

公开(公告)号：US10862031B2

公开(公告)日：2020-12-08

申请号：US16289733

申请日：2019-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Chao Lin ,  Jui-Ming Chen ,  Shao-Ming Yu ,  Tung Ying Lee ,  Yu-Sheng Chen

IPC: H01L45/00 ,  H01L27/24

Abstract: In some embodiments, the present disclosure relates to an integrated chip including a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure upon temperature changes. A top electrode is disposed over an upper surface of the phase change material. A via electrically contacts a top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.

公开(公告)号：US10818777B2

公开(公告)日：2020-10-27

申请号：US16837853

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Chiang ,  Chen-Feng Hsu ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Yu-Lin Yang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/3105

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

公开(公告)号：US10797174B2

公开(公告)日：2020-10-06

申请号：US16104692

申请日：2018-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Tai Chang ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Tzu-Chung Wang ,  Chia-Cheng Ho ,  Ming-Shiang Lin ,  Tzu-Chiang Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/033 ,  H01L21/02 ,  H01L23/532

Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.

公开(公告)号：US20200273997A1

公开(公告)日：2020-08-27

申请号：US16874539

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Ming-Shiang Lin ,  Chia-Cheng Ho ,  Jin Cai ,  Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US20200075718A1

公开(公告)日：2020-03-05

申请号：US16598275

申请日：2019-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/775 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

公开(公告)号：US20240387360A1

公开(公告)日：2024-11-21

申请号：US18786693

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Bo-Jiun Lin

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.

公开(公告)号：US12094771B2

公开(公告)日：2024-09-17

申请号：US17883986

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Jiun Lin ,  Yu Chao Lin ,  Tung Ying Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L29/66795

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

公开(公告)号：US11925127B2

公开(公告)日：2024-03-05

申请号：US17812773

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Yu Chao Lin ,  Shao-Ming Yu

IPC: H10N70/00

CPC classification number: H10N70/063 ,  H10N70/021 ,  H10N70/841 ,  H10N70/8828

Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.

公开(公告)号：US11849655B2

公开(公告)日：2023-12-19

申请号：US17383726

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung Ying Lee ,  Shao-Ming Yu ,  Kai-Tai Chang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/8418 ,  H10B63/24 ,  H10N70/011

Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.