NOVEL MEMORY DEVICE
    11.
    发明申请

    公开(公告)号:US20210090672A1

    公开(公告)日:2021-03-25

    申请号:US17111323

    申请日:2020-12-03

    Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.

    LOW-DROPOUT REGULATOR CIRCUIT
    12.
    发明申请

    公开(公告)号:US20180150090A1

    公开(公告)日:2018-05-31

    申请号:US15494329

    申请日:2017-04-21

    CPC classification number: G05F1/56

    Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

    MEMORY DEVICE AND REFERENCE CIRCUIT THEREOF

    公开(公告)号:US20220115051A1

    公开(公告)日:2022-04-14

    申请号:US17559998

    申请日:2021-12-22

    Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.

    LOW-DROPOUT REGULATOR CIRCUIT
    15.
    发明申请

    公开(公告)号:US20210294368A1

    公开(公告)日:2021-09-23

    申请号:US17339818

    申请日:2021-06-04

    Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

    LOW-DROPOUT REGULATOR CIRCUIT
    16.
    发明申请

    公开(公告)号:US20200150703A1

    公开(公告)日:2020-05-14

    申请号:US16738963

    申请日:2020-01-09

    Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

    NOVEL MEMORY DEVICE
    18.
    发明申请
    NOVEL MEMORY DEVICE 审中-公开

    公开(公告)号:US20190221276A1

    公开(公告)日:2019-07-18

    申请号:US16159214

    申请日:2018-10-12

    CPC classification number: G11C16/3459 G11C16/10 G11C16/26

    Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.

    Selective Error Correction in a Data Storage Device

    公开(公告)号:US20170329669A1

    公开(公告)日:2017-11-16

    申请号:US15153358

    申请日:2016-05-12

    CPC classification number: G06F11/1068 G06F11/1048 G11C29/52 G11C2029/0411

    Abstract: The present disclosure discloses a data storage device having error detection and correction capabilities. The data storage device includes an information encoder/decoder having error checking circuitry to determine whether one or more errors present in an input datastream. When the one or more errors are present in the input datastream, the information encoder/decoder activates error correction circuitry to detect a location one to correct the one or more errors when present in the input datastream. Otherwise, when the one or more errors are not present in the input datastream, the information encoder/decoder deactivates the error correction circuitry. This activation and deactivation conserves power when compared to conventional data storage devices. Any error correction circuitry, if present, in these conventional data storage devices continuously remain active even when the one or more errors are not present in the input datastream.

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