公开(公告)号：US20170213743A1

公开(公告)日：2017-07-27

申请号：US15182291

申请日：2016-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Chun Pan ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/31051 ,  H01L21/02164 ,  H01L21/02205 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

公开(公告)号：US10522365B2

公开(公告)日：2019-12-31

申请号：US15182291

申请日：2016-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Chun Pan ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/84

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.

公开(公告)号：US09711374B2

公开(公告)日：2017-07-18

申请号：US13916827

申请日：2013-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  Chih-Yu Chang ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461 ,  H01L21/321 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/3212 ,  H01L21/02065 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/32105 ,  H01L29/66545

Abstract: Embodiments of cleaning a surface of a polysilicon layer during a chemical mechanical polishing (CMP) process are provided. The method includes providing a substrate, and forming a gate structure on the substrate, and the gate structure includes a polysilicon layer. The method further includes forming an inter-layer dielectric layer (ILD) over the gate structure. The method also includes performing a CMP process to planarize the inter-layer dielectric layer (ILD) and to expose the polysilicon layer, and the CMP process includes: providing an oxidation solution to a surface of the substrate to perform an oxidation operation to form an oxide layer on the polysilicon layer; and providing a cleaning solution to the surface of the substrate to perform a cleaning operation.

公开(公告)号：US20150187594A1

公开(公告)日：2015-07-02

申请号：US14141028

申请日：2013-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/31055 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66545

Abstract: A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底上形成伪栅极，在虚拟栅极上沉积第一介电层，化学机械抛光以将第一介电层退回到虚拟栅极的高度，蚀刻以使第一电介质 在栅极的高度以下，在第一介电层上沉积一个或多个附加电介质层，以及化学机械抛光以将一个或多个另外的介电层退回到栅极的高度。 该方法提供了集成电路器件，其具有金属栅极电极和栅极电平处的包括封盖层的级间电介质。 封盖层抵抗蚀刻并通过替换浇口工艺保持浇口高度。

公开(公告)号：US20240105460A1

公开(公告)日：2024-03-28

申请号：US18524896

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L21/31053 ,  H01L21/30625 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/32139

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

公开(公告)号：US11854821B2

公开(公告)日：2023-12-26

申请号：US17220595

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Hao Tu ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/3105 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/31053 ,  H01L21/30625 ,  H01L21/823437 ,  H01L21/823456 ,  H01L21/28123 ,  H01L21/32139

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

公开(公告)号：US09922837B2

公开(公告)日：2018-03-20

申请号：US15058956

申请日：2016-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wen Liu ,  Che-Hao Tu ,  Po-Chin Nien ,  William Weilun Hong ,  Ying-Tsung Chen

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/66 ,  H01L23/544 ,  H01L21/67 ,  H01L21/321

CPC classification number: H01L21/30625 ,  B24B37/30 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/67092 ,  H01L22/12 ,  H01L22/26 ,  H01L23/544 ,  H01L2223/54493

Abstract: A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The method further includes, after measuring the wafer, performing a Chemical Mechanical Polishing (CMP) process to a first side of the wafer, and during application of the CMP process, applying additional pressure to a region of the wafer, the region comprising an asymmetric part of the wafer, the region including at least a part of the first portion of the wafer.

公开(公告)号：US09209040B2

公开(公告)日：2015-12-08

申请号：US14052687

申请日：2013-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Min Lin ,  Wei-Lun Hong ,  Ying-Tsung Chen ,  Liang-Guang Chen

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/31055 ,  H01L21/02236 ,  H01L21/31053 ,  H01L21/76224

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a first cushion layer, a second cushion layer and an insulating filler. The first cushion layer is peripherally enclosed by the semiconductor substrate, the second cushion layer is peripherally enclosed by the first cushion layer, and insulating filler is peripherally enclosed by the second cushion layer. A method for fabricating the semiconductor device is also provided herein.

Abstract translation: 半导体器件包括半导体衬底和沟槽隔离。 沟槽隔离位于半导体衬底中，并且包括第一缓冲层，第二缓冲层和绝缘填料。 第一缓冲层由半导体衬底周边封闭，第二缓冲层由第一缓冲层周边封闭，绝缘填料由第二缓冲层周边封闭。 本文还提供了一种用于制造半导体器件的方法。