公开(公告)号：US20230275142A1

公开(公告)日：2023-08-31

申请号：US18313190

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Jui-Ping Chuang ,  Chen-Hsiang Lu ,  Yu-Cheng Liu ,  Wei-Ting Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/42372 ,  H01L21/823814 ,  H01L21/823857 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7848 ,  H01L29/7851 ,  H01L21/31111 ,  H01L21/76224

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

公开(公告)号：US20200312985A1

公开(公告)日：2020-10-01

申请号：US16902190

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Jui-Ping Chuang ,  Chen-Hsiang Lu ,  Yu-Cheng Liu ,  Wei-Ting Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/762

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

公开(公告)号：US20200303204A1

公开(公告)日：2020-09-24

申请号：US16895525

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hao Chen ,  Yu-Shu Chen ,  Yu-Cheng Liu

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

公开(公告)号：US10020184B2

公开(公告)日：2018-07-10

申请号：US15454134

申请日：2017-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Ping Hong ,  Yu-Cheng Liu

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/67 ,  H01J37/32 ,  B08B7/00 ,  B08B9/08

CPC classification number: H01L21/02071 ,  B08B7/0035 ,  B08B9/0865 ,  C23C16/4405 ,  H01J37/3244 ,  H01J37/32834 ,  H01J37/32853 ,  H01J37/32862 ,  H01J37/32871 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/02041 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/02334 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/67069 ,  H01L21/76802 ,  H01L21/76814

Abstract: A method for cleaning a substrate is provided. The method includes providing a substrate. Metal compound residues are formed over the substrate. The method includes exposing the substrate to an organic plasma to volatilize the metal compound residues. The organic plasma is generated from a gas. The gas includes an organic gas, and the organic gas is made of a hydrocarbon compound or an alcohol compound.

公开(公告)号：US10002790B2

公开(公告)日：2018-06-19

申请号：US15243663

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yungtzu Chen ,  Yu-Shu Chen ,  Yu-Cheng Liu

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L21/76879 ,  H01L21/02126 ,  H01L21/02186 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L2221/1063

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a semiconductor substrate and forming a hard mask layer over the material layer. The hard mask layer contains metal. The method also includes forming an opening in the hard mask layer using a plasma etching process, and a gas mixture used in the plasma etching process includes a nitrogen-containing gas, a halogen-containing gas, and a carbon-containing gas. The method further includes etching the material layer through the opening in the hard mask layer to form a feature opening in the material layer.

公开(公告)号：US09892957B2

公开(公告)日：2018-02-13

申请号：US14659170

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Wei-Ting Chen ,  Che-Cheng Chang ,  Chen-Hsiang Lu ,  Yu-Cheng Liu

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76804 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76832 ,  H01L23/53295

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure includes a second dielectric layer over the first dielectric layer. The first dielectric layer and the second dielectric layer are made of different materials. The semiconductor device structure includes a conductive via structure passing through the first dielectric layer and penetrating into the second dielectric layer. The conductive via structure has a first portion and a second portion. The first portion and the second portion are in the first dielectric layer and the second dielectric layer respectively. The first portion has a first end portion facing the substrate. A first width of the first end portion is greater than a second width of the second portion.

公开(公告)号：US09735028B2

公开(公告)日：2017-08-15

申请号：US14789337

申请日：2015-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Hung-Hao Chen ,  Yu-Shu Chen ,  Yu-Cheng Liu

IPC: H01L21/311 ,  H01L23/48 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/31144 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/53295

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

公开(公告)号：US09559205B2

公开(公告)日：2017-01-31

申请号：US14725118

申请日：2015-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Che-Cheng Chang ,  Jui-Ping Chuang ,  Chen-Hsiang Lu ,  Wei-Ting Chen ,  Yu-Cheng Liu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底上的翅片结构和覆盖翅片结构的一部分的栅极堆叠。 栅堆叠包括功函数层和栅介质层。 半导体器件结构还包括位于半导体衬底上并与栅堆叠相邻的隔离元件。 隔离元件与功函数层和栅极电介质层直接接触，并且隔离元件的较低宽度大于隔离元件的上部宽度。

公开(公告)号：US20220059403A1

公开(公告)日：2022-02-24

申请号：US17453872

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hao Chen ,  Che-Cheng Chang ,  Wen-Tung Chen ,  Yu-Cheng Liu ,  Horng-Huei Tseng

IPC: H01L21/768

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

公开(公告)号：US09842765B2

公开(公告)日：2017-12-12

申请号：US14658525

申请日：2015-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Wei-Ting Chen ,  Che-Cheng Chang ,  Chen-Hsiang Lu ,  Yu-Cheng Liu

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76804 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76832 ,  H01L23/53295

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a trench. The semiconductor device structure includes a conductive line in the trench. The conductive line has a first end portion and a second end portion. The first end portion faces the substrate. The second end portion faces away from the substrate. A first width of the first end portion is greater than a second width of the second end portion.