公开(公告)号：US20170317033A1

公开(公告)日：2017-11-02

申请号：US15141836

申请日：2016-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hui Wang ,  Chih-Hung Cheng ,  Yung-Chi Lin ,  Wen-Chih Chiou

IPC: H01L23/544 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/3105 ,  H01L21/6835 ,  H01L24/11 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2224/11002 ,  H01L2224/11005

Abstract: A package carrier includes a carrier and a light absorption layer. The light absorption layer is disposed on the carrier. The light absorption layer includes a notch at the periphery of the carrier, and the notch is light transmissive so as to expose the carrier to light in a normal direction of the carrier. A semiconductor manufacturing process is also provided.

公开(公告)号：US20250062204A1

公开(公告)日：2025-02-20

申请号：US18404266

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Zuo Tsai ,  Ming-Tsu Chung ,  Yang-Chih Hsueh ,  Yung-Chi Lin

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/16 ,  H01L23/528

Abstract: A package includes a first die over and bonded to a first side of a second die, where the second die includes a first substrate, a first interconnect structure over the first substrate, a seal ring disposed within the first interconnect structure, first dummy through substrate vias (TSVs) extending through edge regions of the first substrate of the second die and in physical contact with the seal ring, and functional TSVs extending through a central region of the first substrate of the second die.

公开(公告)号：US20250062136A1

公开(公告)日：2025-02-20

申请号：US18513957

申请日：2023-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Yung-Chi Lin ,  Yan-Zuo Tsai ,  Yang-Chih Hsueh ,  Ming-Shih Yeh

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.

公开(公告)号：US20240379505A1

公开(公告)日：2024-11-14

申请号：US18314356

申请日：2023-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Kuang-Wei Cheng ,  Yung-Chi Lin

IPC: H01L23/495 ,  H01L21/18 ,  H01L21/32 ,  H01L21/3213

Abstract: A method includes forming feature for a first package component, and the forming the feature includes a planarization process to level a top surface of the feature. A silicon-containing dielectric layer is deposited over and contacting the feature, and as a surface feature of the first package component. A second package component is bonded to the silicon-containing dielectric layer through fusion bonding. The silicon-containing dielectric layer has a same thickness in both steps of the depositing and the fusion bonding.

公开(公告)号：US20240363359A1

公开(公告)日：2024-10-31

申请号：US18308266

申请日：2023-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Yung-Chi Lin ,  Yen-Ming Chen

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/3213

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/32137

Abstract: A method includes forming a patterned treating mask over a first surface dielectric layer of a first package component, wherein portions of the first surface dielectric layer are exposed through the patterned treating mask, performing a selective plasma treatment on the portions of the first surface dielectric layer that are exposed through the patterned treating mask to form treated portions, removing the patterned treating mask, and bonding a second surface dielectric layer in a second package component to the first surface dielectric layer.

公开(公告)号：US20240312836A1

公开(公告)日：2024-09-19

申请号：US18184968

申请日：2023-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Yung-Chi Lin ,  Yi-Hsiu Chen

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L21/76837 ,  H01L21/30604 ,  H01L21/76802 ,  H01L21/78 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/05 ,  H01L2224/05571

Abstract: A method includes bonding an integrated circuit die to a carrier substrate, forming a gap-filling dielectric around the integrated circuit die and along the edge of the carrier substrate, performing a bevel clean process to remove portions of the gap-filling dielectric from the edge of the carrier substrate, after performing the bevel clean process, depositing a first bonding layer on the gap-filling dielectric and the integrated circuit die, forming a first dielectric layer on an outer sidewall of the first bonding layer, an outer sidewall of the gap-filling dielectric, and the first outer sidewall of the carrier substrate; and bonding a wafer to the first dielectric layer and the first bonding layer, wherein the wafer comprises a semiconductor substrate and a second dielectric layer on an outer sidewall of the semiconductor substrate.

公开(公告)号：US11855067B2

公开(公告)日：2023-12-26

申请号：US17884096

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yung-Chi Lin ,  Wen-Chih Chiou

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08146 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/33519 ,  H01L2224/80006 ,  H01L2224/8083 ,  H01L2224/83005 ,  H01L2224/8383 ,  H01L2224/83896 ,  H01L2224/92142 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

公开(公告)号：US20220392884A1

公开(公告)日：2022-12-08

申请号：US17884096

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yung-Chi Lin ,  Wen-Chih Chiou

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065

Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

公开(公告)号：US20220367407A1

公开(公告)日：2022-11-17

申请号：US17869977

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/3213 ,  H01L25/065 ,  H01L25/00 ,  B23K26/362

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

公开(公告)号：US11437344B2

公开(公告)日：2022-09-06

申请号：US17019913

申请日：2020-09-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/3213 ,  H01L25/00 ,  B23K26/362

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.