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公开(公告)号：US12227410B2
公开(公告)日：2025-02-18
申请号：US18404922
申请日：2024-01-05
Inventor： Po Chen Yeh , Yi-Hsien Chang , Fu-Chun Huang , Ching-Hui Lin , Chiahung Liu , Shih-Fen Huang , Chun-Ren Cheng
Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.
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公开(公告)号：US20240393291A1
公开(公告)日：2024-11-28
申请号：US18789997
申请日：2024-07-31
Inventor： Ching-Hui Lin , Chun-Ren CHENG , Shih-Fen HUANG , Fu-Chun HUANG
IPC: G01N27/414 , B01L3/00 , G01N27/30
Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.
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公开(公告)号：US20240324463A1
公开(公告)日：2024-09-26
申请号：US18679537
申请日：2024-05-31
Inventor： Ching-Hui Lin , Chun-Ren Cheng , Shih-Fen Huang , Fu-Chun Huang
CPC classification number: H10N30/302 , G01N27/4141 , H10N30/05 , H10N30/08 , H10N30/878 , H10N30/88
Abstract: In some embodiments, a piezoelectric biosensor is provided. The piezoelectric biosensor includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A sensing reservoir is disposed over the piezoelectric structure and exposed to an ambient environment, where the sensing reservoir is configured to collect a fluid comprising a number of bio-entities.
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公开(公告)号：US20230240079A1
公开(公告)日：2023-07-27
申请号：US17834274
申请日：2022-06-07
Inventor： Chun-Ren Cheng , Ching-Hui Lin , Fu-Chun Huang , Chao-Hung Chu , Po-Chen Yeh
IPC: H01L27/11509 , H01L23/535 , H01L27/11507
CPC classification number: H01L27/11509 , H01L23/535 , H01L27/11507
Abstract: A semiconductor structure includes a first die, a second die, and an inter die via (IDV). The first die includes an interconnection structure and a CMOS device electrically connected to the interconnection structure. The second die includes a memory element including a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein a peripheral region of the ferroelectric layer is exposed by and surrounding the second electrode from a top view perspective. The IDV electrically connects the interconnection structure of the first die to the memory element of the second die.
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15.发明申请公开(公告)号：US20210383972A1
公开(公告)日：2021-12-09
申请号：US17411416
申请日：2021-08-25
Inventor： Anderson Lin , Chun-Ren Cheng , Chi-Yuan Shih , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Fu-Chun Huang , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
IPC: H01G4/012 , H01G4/228 , H01G4/12 , H01L21/3213 , H01L21/311 , H01L49/02 , H01L41/113 , H01L41/083 , H01L41/047
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.
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Patent Agency Ranking
公开(公告)号：US20200350311A1
公开(公告)日：2020-11-05
申请号：US16923925
申请日：2020-07-08
Inventor： Fu-Chun Huang , Ching-Hui Lin , Chun-Ren Cheng , Shih-Fen Huang , Alexander Kalnitsky
IPC: H01L27/07 , H01L21/762 , H01L21/8234 , H01L29/06 , H01L49/02
Abstract: A method for manufacturing a semiconductor structure is provided, wherein the method includes the following operations. A substrate having a transistor is received, wherein the transistor includes a channel region and a gate on a first side of the channel region. A second side of the channel region of the transistor is exposed, wherein the second side is opposite to the first side. A metal oxide is formed on the second side of the channel region of the transistor, wherein the metal oxide contacts the channel region and is exposed to the environment. A semiconductor structure and an operation of a semiconductor structure thereof are also provided.
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公开(公告)号：US09810689B2
公开(公告)日：2017-11-07
申请号：US15581673
申请日：2017-04-28
Inventor： Ching-Hui Lin , Chun-Ren Cheng , Shih-Fen Huang , Yi-Hsien Chang
IPC: H01L51/05 , G01N27/414 , G01N33/543 , H01L29/78 , C12Q1/00 , H01L51/00 , H01L29/66
CPC classification number: G01N33/5438 , C12Q1/006 , G01N27/414 , G01N27/4145 , G01N27/4148 , H01L29/66484 , H01L29/7831 , H01L29/7832 , H01L51/0093 , H01L51/0512
Abstract: Dual-gate ion-sensitive field effect transistors (ISFETs) for disease diagnostics are disclosed herein. An exemplary dual-gate ISFET includes a gate structure and a fluidic gate structure disposed over opposite surfaces of a device substrate. The gate structure is disposed over a channel region defined between a source region and a drain region in the device substrate. The fluidic gate structure includes a sensing well that is disposed over the channel region. The sensing well includes a sensing layer and an electrolyte solution. The electrolyte solution includes a constituent that can react with a product of an enzymatic reaction that occurs when an enzyme-modified detection mechanism detects an analyte. The sensing layer can react with a first ion generated from the enzymatic reaction and a second ion generated from a reaction between the product of the enzymatic reaction and the constituent, such that the dual-gate ISFET generates an enhanced electrical signal.
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公开(公告)号：US20170227533A1
公开(公告)日：2017-08-10
申请号：US15581673
申请日：2017-04-28
Inventor： Ching-Hui Lin , Chun-Ren Cheng , Shih-Fen Huang , Yi-Hsien Chang
IPC: G01N33/543 , C12Q1/00 , G01N27/414 , H01L29/78
CPC classification number: G01N33/5438 , C12Q1/006 , G01N27/414 , G01N27/4145 , G01N27/4148 , H01L29/66484 , H01L29/7831 , H01L29/7832 , H01L51/0093 , H01L51/0512
Abstract: Dual-gate ion-sensitive field effect transistors (ISFETs) for disease diagnostics are disclosed herein. An exemplary dual-gate ISFET includes a gate structure and a fluidic gate structure disposed over opposite surfaces of a device substrate. The gate structure is disposed over a channel region defined between a source region and a drain region in the device substrate. The fluidic gate structure includes a sensing well that is disposed over the channel region. The sensing well includes a sensing layer and an electrolyte solution. The electrolyte solution includes a constituent that can react with a product of an enzymatic reaction that occurs when an enzyme-modified detection mechanism detects an analyte. The sensing layer can react with a first ion generated from the enzymatic reaction and a second ion generated from a reaction between the product of the enzymatic reaction and the constituent, such that the dual-gate ISFET generates an enhanced electrical signal.
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19.发明授权公开(公告)号：US11984261B2
公开(公告)日：2024-05-14
申请号：US17411416
申请日：2021-08-25
Inventor： Anderson Lin , Chun-Ren Cheng , Chi-Yuan Shih , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Fu-Chun Huang , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
IPC: H01G4/012 , H01G4/12 , H01G4/228 , H01L21/311 , H01L21/3213 , H01L41/047 , H01L41/083 , H01L41/113 , H01L49/02 , H10N30/30 , H10N30/50 , H10N30/87
CPC classification number: H01G4/012 , H01G4/12 , H01G4/228 , H01L21/31111 , H01L21/32139 , H01L28/60 , H10N30/302 , H10N30/501 , H10N30/508 , H10N30/872
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.
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公开(公告)号：US20230302494A1
公开(公告)日：2023-09-28
申请号：US17832937
申请日：2022-06-06
Inventor： Ching-Hui Lin , Yi-Hsien Chang , Chun-Ren Cheng , Fu-Chun Huang , Yi Heng Tsai , Shih-Fen Huang , Chao-Hung Chu , Po-Chen Yeh
CPC classification number: B06B1/0292 , B06B1/0622
Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a dielectric stack disposed on a substrate. The integrated chip structure further includes one or more piezoelectric ultrasonic transducers (PMUTs) and one or more capacitive ultrasonic transducers (CMUTs). The one or more PMUTs include a piezoelectric stack disposed within the dielectric stack over one or more PMUT cavities. The one or more CMUTs include electrodes disposed within the dielectric stack and separated by one or more CMUT cavities. An isolation chamber is arranged within the dielectric stack laterally between the one or more PMUTs and the one or more CMUTs. The isolation chamber vertically extends past at least a part of both the one or more PMUTs and the one or more CMUTs.
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