公开(公告)号：US20150206875A1

公开(公告)日：2015-07-23

申请号：US14158547

申请日：2014-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L27/088 ,  H01L21/324 ,  H01L21/02 ,  H01L29/161 ,  H01L29/165 ,  H01L29/16 ,  H01L21/8234

CPC分类号： H01L29/1054 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7854

摘要： A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor material, replacing a first portion of at least one of the fins with a second semiconductor material, and distributing the second semiconductor material from the first portion to a second portion of the at least one of the fins.

摘要翻译： 一种半导体装置的制造方法，其特征在于，包括：提供基板，形成具有第一半导体材料的多个散热片，用第二半导体材料代替至少一个所述散热片的第一部分，将所述第二半导体材料从 所述第一部分到所述至少一个所述翅片的第二部分。

公开(公告)号：US09087902B2

公开(公告)日：2015-07-21

申请号：US13779015

申请日：2013-02-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/70 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/417 ,  H01L29/778 ,  H01L29/165 ,  H01L29/43 ,  H01L29/06

CPC分类号： H01L29/7842 ,  H01L21/02532 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/157 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

摘要： A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

摘要翻译： 一种器件包括衬底和衬底的一部分上的绝缘区域。 第一半导体区域在绝缘区域之间并且具有第一导带。 第二半导体区域在第一半导体区域的上方并且邻接，其中第二半导体区域包括高于绝缘区域的顶表面的上部，以形成半导体鳍片。 半导体鳍具有拉伸应变，并且具有比第一导带低的第二导带。 第三半导体区域在半导体鳍片的上表面和侧壁的上方邻接，其中第三半导体区域具有比第二导带高的第三导带。

公开(公告)号：US20140220753A1

公开(公告)日：2014-08-07

申请号：US14251780

申请日：2014-04-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  You-Ru Lin ,  Cheng-Tien Wan ,  Cheng-Hsien Wu ,  Chih-Hsin Ko

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/762

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02634 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/7853

摘要： A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.

摘要翻译： FinFET包括形成在衬底中的隔离区域，形成在衬底上的斗篷形有源区域，其中斗篷形有源区域具有突出于隔离区域顶表面上方的上部。 此外，FinFET包括包围斗篷形有源区的通道的栅电极。

公开(公告)号：US20240312990A1

公开(公告)日：2024-09-19

申请号：US18677372

申请日：2024-05-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Shuo CHEN ,  Chia-Der Chang ,  Yi-Jing Lee

IPC分类号： H01L27/088 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/092

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0924 ,  H01L21/31116 ,  H01L21/32135 ,  H01L27/0928

摘要： A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.

公开(公告)号：US20210328047A1

公开(公告)日：2021-10-21

申请号：US17364623

申请日：2021-06-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Jing Lee ,  Ming-Hua Yu

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/04 ,  H01L27/092

摘要： In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

公开(公告)号：US20190341472A1

公开(公告)日：2019-11-07

申请号：US15967672

申请日：2018-05-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Ming-Hua Yu

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/167 ,  H01L29/36

摘要： A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

公开(公告)号：US20190341471A1

公开(公告)日：2019-11-07

申请号：US16511580

申请日：2019-07-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Ming-Hua Yu

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/78

摘要： A method includes forming first spacers on opposing sidewalls of a first fin, where the first fin protrudes above a substrate, recessing the first fin to form a first recess between the first spacers, and treating the first spacers using a baking process, where treating the first spacers changes a profile of the first spacers. The method further includes epitaxially growing a first semiconductor material over a top surface of the first fin after treating the first spacers.

公开(公告)号：US10170375B2

公开(公告)日：2019-01-01

申请号：US15404937

申请日：2017-01-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/10

摘要： A semiconductor device includes a PMOS FinFET and an NMOS FinFET. The PMOS FinFET includes a substrate, a silicon germanium layer disposed over the substrate, a silicon layer disposed over the silicon germanium layer, and a PMOS fin disposed over the silicon layer. The PMOS fin contains silicon germanium. The NMOS FinFET includes the substrate, a silicon germanium oxide layer disposed over the substrate, a silicon oxide layer disposed over the silicon germanium oxide layer, and an NMOS fin disposed over the silicon oxide layer. The NMOS fin contains silicon. The silicon germanium oxide layer and the silicon oxide layer collectively define a concave recess in a horizontal direction. The concave recess is partially disposed below the NMOS fin.

公开(公告)号：US20170352596A1

公开(公告)日：2017-12-07

申请号：US15687753

申请日：2017-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Cheng-Hsien Wu ,  Chih-Hsin Ko ,  Clement Hsingjen Wann

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L29/778 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/417 ,  H01L29/165 ,  H01L29/161 ,  H01L29/15 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/321 ,  H01L29/78 ,  H01L29/43

CPC分类号： H01L29/7842 ,  H01L21/02532 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/157 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

摘要： A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

公开(公告)号：US20170309730A1

公开(公告)日：2017-10-26

申请号：US15647820

申请日：2017-07-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  You-Ru Lin ,  Cheng-Tien Wan ,  Cheng-Hsien Wu ,  Chih-Hsin Ko

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3065

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02634 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/7853

摘要： A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.