Abstract:
A device includes a first word line, a resistive random access memory (RRAM) cell, a second word line, and a charge pump circuit. The RRAM cell is coupled to the first word line and is not formed. The charge pump circuit is coupled to the second word line and is configured to provide a negative voltage. Methods of forming the device are also disclosed.
Abstract:
According to another embodiment, a method of reset operation for a resistive random access memory (RRAM) array, having a first RRAM connected to a first word line and a second RRAM connected to a second word line, is provided. A first electrical resistance between the first word line and a word line voltage source is lower than a second electrical resistance between the second word line and the word line voltage source. The method includes: providing a first voltage by using the word line voltage source for resetting the first RRAM; and providing a second voltage by using the word line voltage source for resetting the second RRAM, wherein the first voltage for resetting the first RRAM is lower than the second voltage for resetting the second RRAM.
Abstract:
A device structure includes a first series connection of a first phase change memory (PCM) switch and a second PCM switch. The first PCM switch includes a first heater line, a first PCM line, and a first contact electrode and a second contact electrode located on the first heater line. The second PCM switch includes a second heater line, a second PCM line, and a third contact electrode and a fourth contact electrode located on the second heater line. The second contact electrode is electrically connected to the third contact electrode. The fourth contact electrode is electrically grounded. One of the first contact electrode and the second contact electrode includes an radio-frequency (RF) signal input port. Another of the first contact electrode and the second contact electrode comprises an RF signal output port. The device structure may function as a combination PCM switch that decreases noise level during signal transmission.
Abstract:
A device structure includes semiconductor devices located on a substrate; metal interconnect structures located in dielectric material layers overlying the semiconductor devices; and a non-Ohmic voltage-triggered switch including a first switch electrode that is electrically connected to one of the semiconductor devices through a subset of the metal interconnect structures, a second switch electrode, and a non-Ohmic switching material portion providing a non-Ohmic current-voltage characteristics and in contact with the first switch electrode and the second switch electrode. The non-Ohmic voltage-triggered switch may be used as an electrostatic discharge (ESD) switch.
Abstract:
A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.
Abstract:
According to one embodiment, a method of RRAM operations is provided. The method includes the following operations: providing a first voltage difference across a resistor of the RRAM during a read operation; and providing a second voltage difference across the resistor of the RRAM during a reset operation, wherein the first voltage difference has the same polarity as the second voltage difference.
Abstract:
A device structure includes a first electrode overlying a substrate; a node dielectric contacting the first electrode and including a dielectric material having a dielectric constant greater than 30; and a second electrode contacting the node dielectric. A first one of the first electrode and the second electrode includes a first catalytic metal plate in direct contact with the node dielectric and having a first electronegativity that is not greater than an electronegativity of molybdenum.
Abstract:
Phase change material (PCM) switches and methods of fabrication thereof that provide improved thermal confinement within a phase change material layer. A PCM switch may include a dielectric capping layer between a heater pad and the phase change material layer of the PCM switch that is laterally-confined such opposing sides of the dielectric capping layer the heater pad may form continuous surfaces extending transverse to the signal transmission pathway across the PCM switch. Heat transfer from the heater pad through the dielectric capping layer to the phase change material layer may be predominantly vertical, with minimal thermal dissipation along a lateral direction. The localized heating of the phase change material may improve the efficiency of the PCM switch enabling lower bias voltages, minimize the formation of regions of intermediate resistivity in the PCM switch, and improve the parasitic capacitance characteristics of the PCM switch.
Abstract:
A semiconductor structure may be located over a substrate, and may include a parallel connection of a first component and a second component. The first component includes a series connection of a diode and a capacitor that is selected from a metal-ferroelectric-metal capacitor and a metal-antiferroelectric-metal capacitor. The second component includes a battery structure. The semiconductor structure may be used as a combination of an energy harvesting device and an energy storage structure that utilizes heat from adjacent semiconductor devices or from other heat sources.
Abstract:
A semiconductor structure may include semiconductor devices located on a substrate, metal interconnect structures that are located within dielectric material layers overlying the semiconductor devices and are electrically connected to the semiconductor devices, and an energy harvesting device located over the metal interconnect structures and comprising a Schottky barrier diode, a first diode electrode located on a first side of the Schottky barrier diode, and a second diode electrode connected to a second side of the Schottky barrier diode.