公开(公告)号：US08420473B2

公开(公告)日：2013-04-16

申请号：US12960586

申请日：2010-12-06

申请人： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

发明人： Takashi Ando ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7848

摘要： A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.

摘要翻译： 同时制造n型和p型场效应晶体管的方法可以包括在覆盖第一有源半导体区域的电介质区域中的第一开口中形成具有与栅极电介质层相邻的第一栅极金属层的第一替代栅极。 包括第二栅极金属层的第二替代栅极可以在覆盖在第二有源半导体区域上的电介质区域中的第二开口中邻近栅极电介质层形成。 第一和第二栅极金属层的至少一部分可以沿其厚度的方向堆叠并且通过至少阻挡金属层彼此分离。 由该方法产生的NFET可以包括第一有源半导体区域，其中的源极/漏极区域和第一替换栅极，并且由该方法产生的PFET可以包括第二有源半导体区域，其中的源/漏区域和第二替换 门。

公开(公告)号：US20120299123A1

公开(公告)日：2012-11-29

申请号：US13570388

申请日：2012-08-09

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L29/78

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US08274116B2

公开(公告)日：2012-09-25

申请号：US12619209

申请日：2009-11-16

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L21/70

CPC分类号： H01L21/823857 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651

摘要： A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.

摘要翻译： 用于CMOS器件的高k金属栅极堆叠和结构以及用于形成器件的方法。 栅极堆叠包括形成在半导体衬底上的锗（Ge）材料层，形成在Ge材料层上的扩散阻挡层，在扩散阻挡层上形成的具有大于约3.9的高介电常数的高k电介质，以及 形成在高k电介质层上方的导电电极层。

公开(公告)号：US20110309455A1

公开(公告)日：2011-12-22

申请号：US12816605

申请日：2010-06-16

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US20090181505A1

公开(公告)日：2009-07-16

申请号：US12013846

申请日：2008-01-14

申请人： Takashi Ando ,  Eduard A. Cartier ,  Changhwan Choi ,  Elizabeth A. Duch ,  Bruce B. Doris ,  Young-Hee Kim ,  Vijay Narayanan ,  James Pan ,  Vamsi K. Paruchuri

发明人： Takashi Ando ,  Eduard A. Cartier ,  Changhwan Choi ,  Elizabeth A. Duch ,  Bruce B. Doris ,  Young-Hee Kim ,  Vijay Narayanan ,  James Pan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.

摘要翻译： 在一个实施例中，本发明是用于制造高性能带边互补金属氧化物半导体器件的方法和装置。 用于制造互补金属氧化物半导体器件的方法的一个实施例包括使用栅极第一工艺制造n型金属氧化物半导体器件，以及使用栅极最后工艺制造p型金属氧化物半导体器件 。

公开(公告)号：US09059314B2

公开(公告)日：2015-06-16

申请号：US13602118

申请日：2012-09-01

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

摘要翻译： 提供了相当于氧化物厚度（EOT）的高k /金属栅极叠层，其中基本上消除了界面层的电容瓶颈，对器件沟道中载流子的迁移率的影响最小。 在一个实施例中，通过将界面层的介电常数提高到大于原始形成的界面层的值，即高k扩散之前的界面层，可实现上述EOT缩放的高k /金属栅极堆叠 材料掺杂元素。 在另一个实施例中，通过从结构中消除界面层来实现上述缩放的高k /金属栅极堆叠。 在另一个实施方案中，上述高k /金属栅极堆叠是通过增加界面层的介电常数和减少/消除界面层来实现的。

公开(公告)号：US08835260B2

公开(公告)日：2014-09-16

申请号：US13547792

申请日：2012-07-12

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L21/8234 ,  H01L21/4763 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L21/823857 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66651

摘要： A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.

摘要翻译： 用于CMOS器件的高k金属栅极堆叠和结构以及用于形成器件的方法。 栅极堆叠包括形成在半导体衬底上的锗（Ge）材料层，形成在Ge材料层上的扩散阻挡层，在扩散阻挡层上形成的具有大于约3.9的高介电常数的高k电介质，以及 形成在高k电介质层上方的导电电极层。

公开(公告)号：US08748991B2

公开(公告)日：2014-06-10

申请号：US13550919

申请日：2012-07-17

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Vijay Narayanan

IPC分类号： H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/513 ,  H01L29/78

摘要： A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.

摘要翻译： 用于CMOS器件的高k金属栅极堆叠和结构以及用于形成器件的方法。 栅极堆叠包括具有大于约3.9的高介电常数的高k电介质，与高k电介质接合的锗（Ge）材料层，以及设置在高k电介质或Ge材料上方的导电电极层 层。 栅极堆叠优化了平带电压或阈值电压的偏移，以在p-FET器件中获得高性能。

公开(公告)号：US08735996B2

公开(公告)日：2014-05-27

申请号：US13547772

申请日：2012-07-12

申请人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

发明人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

IPC分类号： H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.

摘要翻译： 提供半导体结构。 该结构包括半导体材料的半导体衬底和具有介电常数大于硅的介电常数介电层的栅极电介质。 栅极电介质位于半导体衬底上。 栅电极邻接栅极电介质。 栅电极包括邻接栅电介质的下金属层，邻接下金属层的扫除金属层，与清扫金属层邻接的上金属层和邻接上金属层的硅层。 清除金属层响应于退火而在上金属层和硅层之间的界面处减少氧化层。

公开(公告)号：US20140004695A1

公开(公告)日：2014-01-02

申请号：US13534573

申请日：2012-06-27

申请人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

发明人： Takashi Ando ,  Unoh Kwon ,  Vijay Narayanan ,  James K. Schaeffer

IPC分类号： H01L21/283

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure is provided. The structure includes a semiconductor substrate of a semiconductor material and a gate dielectric having a high dielectric constant dielectric layer with a dielectric constant greater than silicon. The gate dielectric is located on the semiconductor substrate. A gate electrode abuts the gate dielectric. The gate electrodes includes a lower metal layer abutting the gate dielectric, a scavenging metal layer abutting the lower metal layer, an upper metal layer abutting the scavenging metal layer, and a silicon layer abutting the upper metal layer. The scavenging metal layer reduces an oxidized layer at an interface between the upper metal layer and the silicon layer responsive to annealing.