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    Semiconductor device and semiconductor integrated circuit using the same
    11.
    发明授权
    Semiconductor device and semiconductor integrated circuit using the same 失效
    半导体器件和半导体集成电路使用相同

    公开(公告)号：US07808045B2

    公开(公告)日：2010-10-05

    申请号：US12767548

    申请日：2010-04-26

    申请人： Takayuki Kawahara ,  Masanao Yamaoka

    发明人： Takayuki Kawahara ,  Masanao Yamaoka

    IPC分类号： H01L23/62

    CPC分类号： H01L27/1203 ,  H01L29/78645 ,  H01L29/78648

    摘要： The present invention provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit.In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in the logic circuits having a small load in the logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to the gate input signal.

    摘要翻译： 本发明提供一种可在宽温度范围内工作的高速，低功耗的LSI，其具有根据电路的工作特性专门使用具有后栅的MOS晶体管。 在LSI中，使用具有嵌入的氧化膜层的FD-SOI结构，并且将埋入的氧化膜层的下半导体区域用作后栅。 在逻辑电路块中具有小负载的逻辑电路中的后门的电压响应于块外部的激活而被控制。 栅极和背栅彼此连接的晶体管用于产生背栅极驱动信号的电路，以及具有诸如电路块输出部分的重负载的逻辑电路，并且后门直接根据 到门输入信号。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    13.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20080203403A1

    公开(公告)日：2008-08-28

    申请号：US11960680

    申请日：2007-12-19

    申请人： Takayuki Kawahara ,  Masanao Yamaoka ,  Nobuyuki Sugii

    发明人： Takayuki Kawahara ,  Masanao Yamaoka ,  Nobuyuki Sugii

    IPC分类号： H01L33/00 ,  H01L27/12

    CPC分类号： H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1203 ,  H01L27/153

    摘要： The semiconductor integrated circuit (1) has a memory (4) and a logic circuit (5), which are mixedly palletized on a silicon substrate (2). The memory includes a partially-depleted type nMOS (6) having an SOI structure and formed on UTB (3). The partially-depleted type nMOS has a backgate region (14) under UTB, to which a voltage can be applied independently of a corresponding gate terminal. The logic circuit includes an nMOS (7) and a pMOS (8), and both are of a fully-depleted type, formed on UTB and have an SOI structure. The fully-depleted type nMOS and pMOS have backgate regions (14, 22) under respective UTBs, to which voltages can be applied independently of the corresponding gate terminals

    摘要翻译： 半导体集成电路（1）具有在硅衬底（2）上混合堆垛的存储器（4）和逻辑电路（5）。 存储器包括具有SOI结构并形成在UTB（3）上的部分耗尽型nMOS（6）。 部分耗尽型nMOS在UTB之下具有背栅区域（14），独立于对应的栅极端子可以施加电压。 逻辑电路包括nMOS（7）和pMOS（8），并且它们都是完全耗尽型的，形成在UTB上并具有SOI结构。 完全耗尽型nMOS和pMOS在相应的UTB下具有背栅区域（14,22），可以独立于对应的栅极端子施加电压

    Semiconductor memory device with memory cells operated by boosted voltage
    14.
    发明授权
    Semiconductor memory device with memory cells operated by boosted voltage 有权
    具有由升压电压工作的存储单元的半导体存储器件

    公开(公告)号：US07397693B2

    公开(公告)日：2008-07-08

    申请号：US11657026

    申请日：2007-01-24

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Koichiro Ishibashi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417 ,  G11C11/412 ,  Y10S257/903

    摘要： A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

    摘要翻译： 使用用于低电压操作的SRAM存储单元的存储器被设计为降低构成存储器单元的MOS晶体管的阈值，而不会显着降低静态噪声容限，这是存储单元的操作余量。 为此，作为存储单元的电源电压，从用于存储单元的电源线提供高于外围电路用电源线的电源电压Vdd的电压Vdd'。 由于驱动器MOS晶体管的电导被增加，所以可以在不降低静态噪声容限的情况下减小存储单元内的MOS晶体管的阈值电压。 此外，可以将驱动器MOS晶体管和转移MOS晶体管之间的宽度比设置为1，从而允许存储单元区域的减小。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR
    15.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR 审中-公开
    半导体集成电路及其制造方法

    公开(公告)号：US20080143423A1

    公开(公告)日：2008-06-19

    申请号：US11943095

    申请日：2007-11-20

    申请人： Shigenobu Komatsu ,  Kenichi Osada ,  Masanao Yamaoka ,  Koichiro Ishibashi

    发明人： Shigenobu Komatsu ,  Kenichi Osada ,  Masanao Yamaoka ,  Koichiro Ishibashi

    IPC分类号： H03K3/01 ,  H01L21/8238

    CPC分类号： H01L27/092 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203 ,  H03K19/0027 ,  H03K19/00315

    摘要： The present invention is directed to realize high manufacture yield and compensate variations in threshold voltage of a MOS transistor with small overhead. A semiconductor integrated circuit includes a CMOS circuit for processing an input signal in an active mode, a control switch, and a control memory. The control switch supplies a pMOS body bias voltage and an nMOS body bias voltage to an N well in a pMOS transistor and a P well in an nMOS transistor, respectively, in the CMOS circuit. The control memory stores control information indicating whether or not the pMOS body bias voltage and the nMOS body bias voltage are supplied from the control switch to the N well in the pMOS transistor and the P well in the nMOS transistor, respectively, in the CMOS circuit in the active mode.

    摘要翻译： 本发明旨在实现高制造成品率并补偿具有较小开销的MOS晶体管的阈值电压的变化。 半导体集成电路包括用于处理活动模式中的输入信号的CMOS电路，控制开关和控制存储器。 控制开关分别向CMOS电路中的nMOS晶体管中的pMOS晶体管和P阱中的N阱施加pMOS体偏置电压和nMOS体偏置电压。 控制存储器存储指示pMOS体偏置电压和nMOS体偏置电压是否从控制开关提供到CMOS电路中的nMOS晶体管中的pMOS晶体管和P阱中的N阱的控制信息 处于活动模式。

    Semiconductor device formed on a SOI substrate
    16.
    发明申请
    Semiconductor device formed on a SOI substrate 审中-公开
    形成在SOI衬底上的半导体器件

    公开(公告)号：US20070246767A1

    公开(公告)日：2007-10-25

    申请号：US11812694

    申请日：2007-06-21

    申请人： Kenichi Osada ,  Takayuki Kawahara ,  Masanao Yamaoka

    发明人： Kenichi Osada ,  Takayuki Kawahara ,  Masanao Yamaoka

    IPC分类号： H01L29/76

    CPC分类号： H01L29/78648 ,  G11C11/412 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0928 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/78609 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.

    摘要翻译： 完全耗尽型SOI衬底的MISFETS的阈值不能通过改变杂质密度来控制，就像体硅硅MISFET那样。 因此，难以为每个电路设定合适的阈值。 根据本发明的半导体器件，构成存储单元的P沟道型MISFET的栅电极由N型多晶硅制成，N沟道型MISFET的栅电极由P型多晶硅制成，栅电极为P 通道型和外围电路的N沟道型MISFET和逻辑电路由P型硅锗制成。 对于使用SOI衬底的每个电路，可以实现合适的阈值，从而可以充分利用SOI衬底的特性。