公开(公告)号：US20180204734A1

公开(公告)日：2018-07-19

申请号：US15714169

申请日：2017-09-25

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Helmut Rinck ,  Mike Mittelstaedt

IPC分类号： H01L21/311 ,  H01L21/263

CPC分类号： H01L21/28052 ,  C01G55/00 ,  C01G55/004 ,  H01L21/02068 ,  H01L21/2633 ,  H01L21/28518 ,  H01L21/31122 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823835 ,  H01L23/53242 ,  H01L24/00 ,  H01L28/24 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

公开(公告)号：US20240222470A1

公开(公告)日：2024-07-04

申请号：US18428198

申请日：2024-01-31

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Helmut Rinck ,  Mike Mittelstaedt

IPC分类号： H01L29/66 ,  C01G55/00 ,  H01L21/02 ,  H01L21/263 ,  H01L21/28 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/665 ,  C01G55/00 ,  C01G55/004 ,  H01L21/02068 ,  H01L21/2633 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/31122 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/53242 ,  H01L24/00 ,  H01L28/24 ,  H01L29/4975 ,  H01L29/6659 ,  H01L29/7833 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823835

摘要： A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.

公开(公告)号：US20230184713A1

公开(公告)日：2023-06-15

申请号：US18066206

申请日：2022-12-14

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Ernst Muellner ,  Helmut Rinck ,  Scott Summerfelt ,  Tobias Fritz ,  Baher Haroun

IPC分类号： G01N27/414

CPC分类号： G01N27/4148 ,  G01N27/4146

摘要： In some examples, an integrated circuit comprises: a semiconductor die including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a metallization structure encapsulated in the dielectric layer, in which the semiconductor substrate includes a transistor having a first current terminal, a second current terminal, and a channel region between the first and second current terminals, and the dielectric layer has a sensing side facing away from the semiconductor substrate; an insulation layer on the sensing side; a sensor terminal on the sensing side and over the channel region; and a restriction structure including an opening and a rigid silicon-based fluidic structure, in which the silicon-based fluidic structure is on the sensing side and encapsulates a fluid cavity on the sensing side, the sensor terminal is in the fluid cavity, and the restriction structure is configured to transport a fluid by microfluidic diffusion.

公开(公告)号：US11011381B2

公开(公告)日：2021-05-18

申请号：US16523867

申请日：2019-07-26

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Helmut Rinck

IPC分类号： H01L21/306 ,  H01L21/308 ,  C23F1/44 ,  C23F1/30 ,  H01L21/24

摘要： There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.

公开(公告)号：US20200035500A1

公开(公告)日：2020-01-30

申请号：US16523867

申请日：2019-07-26

申请人： Texas Instruments Incorporated

发明人： Sebastian Meier ,  Helmut Rinck

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L21/24 ,  C23F1/30 ,  C23F1/44

摘要： There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.

公开(公告)号：US09960135B2

公开(公告)日：2018-05-01

申请号：US14665799

申请日：2015-03-23

申请人： Texas Instruments Incorporated

发明人： Helmut Rinck ,  Gernot Bauer ,  Robert Zrile ,  Kai-Alexander Schachtschneider ,  Michael Otte ,  Harald Wiesner

IPC分类号： H01L21/28 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L24/13 ,  H01L23/5226 ,  H01L23/53204 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05558 ,  H01L2224/05657 ,  H01L2224/11005 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01078 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01051

摘要： A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.