公开(公告)号：US08530337B1

公开(公告)日：2013-09-10

申请号：US13530605

申请日：2012-06-22

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  John A. Ott ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  John A. Ott ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/304

CPC分类号： H01L22/12 ,  H01L21/304 ,  H01L21/7806 ,  H01L21/7813

摘要： Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.

公开(公告)号：US08518807B1

公开(公告)日：2013-08-27

申请号：US13530637

申请日：2012-06-22

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/00

CPC分类号： H01L21/31155 ,  H01L21/304 ,  H01L21/7624

摘要： An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.

公开(公告)号：US09041167B2

公开(公告)日：2015-05-26

申请号：US13555271

申请日：2012-07-23

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/00 ,  H01L21/3115 ,  H01L21/762

CPC分类号： H01L21/31155 ,  H01L21/304 ,  H01L21/7624

摘要： An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact.

摘要翻译： 首先提供包括位于基底基板和顶部半导体有源层之间的掩埋绝缘体层的SOI衬底。 然后可以在顶部半导体有源层的一部分上和/或内部形成半导体器件。 掩埋绝缘体层的与埋入绝缘体层的与顶部半导体活性层形成界面的最上表面相对的最底表面可以暴露。 然后，离子可以通过掩埋绝缘体层的最底部的表面注入埋入的绝缘体层的一部分中。 将离子注入到不会干扰埋入的绝缘体层/顶部半导体有源层界面的能量范围内，同时在掩埋的绝缘体层/顶部半导体活性层界面附近保留相当薄的部分隐埋绝缘体层。

公开(公告)号：US08940580B2

公开(公告)日：2015-01-27

申请号：US13544380

申请日：2012-07-09

申请人： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/00

CPC分类号： H01L31/02363 ,  H01L31/0687 ,  H01L31/0693 ,  H01L31/1852 ,  Y02E10/544

摘要： A method for forming a multi junction photovoltaic device includes providing a germanium layer and etching pyramidal shapes in the germanium layer such that (111) facets are exposed to form a textured surface. A first p-n junction is formed on or over the textured surface from III-V semiconductor materials. Another p-n junction is formed over the first p-n junction from III-V semiconductor materials and follows the textured surface.

摘要翻译： 一种用于形成多结光伏器件的方法包括提供锗层并在锗层中蚀刻金字塔形，使得（111）面暴露以形成纹理表面。 在III-V半导体材料的纹理表面上或上方形成第一p-n结。 在III-V半导体材料的第一个p-n结上形成另一个p-n结，并跟随纹理表面。

公开(公告)号：US20130112275A1

公开(公告)日：2013-05-09

申请号：US13290404

申请日：2011-11-07

申请人： Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Bahman Hekmatshoar-Tabari ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/0264 ,  H01L31/18

CPC分类号： H01L31/074 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/26513 ,  H01L31/02167 ,  H01L31/022425 ,  H01L31/022441 ,  H01L31/022466 ,  H01L31/02363 ,  H01L31/02366 ,  H01L31/03044 ,  H01L31/03048 ,  H01L31/0336 ,  H01L31/036 ,  H01L31/0682 ,  H01L31/072 ,  H01L31/18 ,  H01L31/1852 ,  H01L31/1868 ,  H01L31/1884 ,  Y02E10/544

摘要： A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.

公开(公告)号：US20140004654A1

公开(公告)日：2014-01-02

申请号：US13544380

申请日：2012-07-09

申请人： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/18

CPC分类号： H01L31/02363 ,  H01L31/0687 ,  H01L31/0693 ,  H01L31/1852 ,  Y02E10/544

摘要： A method for forming a multi junction photovoltaic device includes providing a germanium layer and etching pyramidal shapes in the germanium layer such that (111) facets are exposed to form a textured surface. A first p-n junction is formed on or over the textured surface from III-V semiconductor materials. Another p-n junction is formed over the first p-n junction from III-V semiconductor materials and follows the textured surface.

摘要翻译： 一种用于形成多结光伏器件的方法包括提供锗层并在锗层中蚀刻金字塔形，使得（111）面暴露以形成纹理表面。 在III-V半导体材料的纹理表面上或上方形成第一p-n结。 在III-V半导体材料的第一个p-n结上形成另一个p-n结，并跟随纹理表面。

公开(公告)号：US08592323B1

公开(公告)日：2013-11-26

申请号：US13555261

申请日：2012-07-23

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  John A. Ott ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  John A. Ott ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/469

CPC分类号： H01L22/12 ,  H01L21/304 ,  H01L21/7806 ,  H01L21/7813

摘要： Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce.

公开(公告)号：US08421521B1

公开(公告)日：2013-04-16

申请号：US13538025

申请日：2012-06-29

申请人： Arjang Hassibi ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Davood Shahrjerdi

发明人： Arjang Hassibi ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Davood Shahrjerdi

IPC分类号： G05F1/10

CPC分类号： H01L29/78648 ,  G01N27/4148

摘要： Embodiments relate to a metal-oxide-semiconductor device including a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes a gate configured to change electrical characteristics based on a sensed chemical characteristic and a source and drain. One of the source and drain is connected to an analysis circuit, and a backgate is connected to an AC voltage source.

摘要翻译： 实施例涉及包括金属氧化物半导体场效应晶体管（MOSFET）的金属氧化物半导体器件。 MOSFET包括被配置为基于感测的化学特性和源极和漏极改变电特性的栅极。 源极和漏极之一连接到分析电路，并且背栅极连接到AC电压源。

公开(公告)号：US08354876B1

公开(公告)日：2013-01-15

申请号：US13550967

申请日：2012-07-17

申请人： Arjang Hassibi ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Davood Shahrjerdi

发明人： Arjang Hassibi ,  Bahman Hekmatshoartabari ,  Ali Khakifirooz ,  Davood Shahrjerdi

IPC分类号： H03K3/01

CPC分类号： H01L29/78648 ,  G01N27/4148

摘要： Embodiments relate to a method including receiving a voltage potential at a gate of a first MOSFET based on a sensed chemical characteristic. The method includes receiving at a backgate of the first MOSFET an AC voltage signal and analyzing, with an analysis circuit connected to one of a first source and a first drain of the MOSFET, the sensed characteristic based on the receiving the voltage potential at the gate of the first MOSFET.

摘要翻译： 实施例涉及一种方法，包括基于感测到的化学特性来接收第一MOSFET的栅极处的电压电位。 该方法包括在第一MOSFET的背栅极处接收AC电压信号，并且利用连接到MOSFET的第一源极和第一漏极之一的分析电路来分析基于在栅极处接收电压电位的感测特性 的第一个MOSFET。

公开(公告)号：US20120205784A1

公开(公告)日：2012-08-16

申请号：US13037944

申请日：2011-03-01

申请人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L29/02 ,  H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

摘要： Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient.

摘要翻译： 使用氢将压缩应变硅在低温下直接外延生长到硅衬底上以设计应变水平。 在这样的生长过程中氢稀释可以变化以提供应变梯度。