公开(公告)号：US4809206A

公开(公告)日：1989-02-28

申请号：US87346

申请日：1987-08-20

申请人： Atsushi Kiuchi ,  Kenji Kaneko ,  Jun Ishida ,  Tetsuya Nakagawa ,  Yoshimune Hagiwara ,  Hirotada Ueda

发明人： Atsushi Kiuchi ,  Kenji Kaneko ,  Jun Ishida ,  Tetsuya Nakagawa ,  Yoshimune Hagiwara ,  Hirotada Ueda

IPC分类号： G06F9/34 ,  G06F7/544 ,  G06F12/02 ,  G06F17/10 ,  H03H17/02 ,  G06F7/38

CPC分类号： G06F7/5443

摘要： This invention relates to an information processing apparatus such as a digital signal processor and is applied particularly suitably to a digital filter.A plurality of data from initial value data till final value data relating to filtering coefficients of a digital filter are stored in a data memory, and are sequentially read out by an increment operation of an address arithmetic unit.A data arithmetic unit executes sequentially product and/or sum operations of a plurality of data that are sequentially read out and digital input signals that are sequentially inputted, to perform digital signal processing.The information processing apparatus is equipped particularly with means, which when an access address starts from an initial value, exceeds a final value and reaches a return address due to the increment operation, returns automatically the access address to the initial value. Therefore, a plurality of data stored in the data memory can be utilized repeatedly.Contrivances are made in order to set the number of a plurality of data that are stored in the data memory for repetition of use, to an arbitrary value.

摘要翻译： 本发明涉及诸如数字信号处理器的信息处理设备，并且特别适用于数字滤波器。 从初始值数据到与数字滤波器的滤波系数相关的最终值数据的多个数据被存储在数据存储器中，并且通过地址运算单元的增量操作被依次读出。 数据运算单元依次执行依次读出的多个数据和顺序输入的数字输入信号的乘积和/或和运算，进行数字信号处理。 该信息处理装置特别地具有如下装置：当访问地址从初始值开始时，由于增量操作而超过最终值并达到返回地址，自动将访问地址返回到初始值。 因此，可以重复使用存储在数据存储器中的多个数据。 为了将存储在用于重复使用的数据存储器中的多个数据的数量设置为任意值，进行了操作。

公开(公告)号：US4740923A

公开(公告)日：1988-04-26

申请号：US799640

申请日：1985-11-19

申请人： Kenji Kaneko ,  Jun Ishida ,  Yoshimune Hagiwara ,  Hitoshi Matsushima ,  Hirotada Ueda

发明人： Kenji Kaneko ,  Jun Ishida ,  Yoshimune Hagiwara ,  Hitoshi Matsushima ,  Hirotada Ueda

IPC分类号： G01R1/067 ,  G01R1/073 ,  H05K13/08 ,  G11C7/00

CPC分类号： G01R1/07328 ,  G01R1/06722 ,  G01R1/07378 ,  H05K13/08

摘要： A memory circuit is divided into a plurality of memory blocks, and an address register and a delay register are disposed in each memory block. Therefore, a read or write operation and a shifting operation of the address for storing data inside a memory matrix can be realized by a pipeline technique, and hence a memory circuit having a high processing speed is obtained.

摘要翻译： 存储器电路被分成多个存储块，并且地址寄存器和延迟寄存器被布置在每个存储块中。 因此，通过流水线技术可以实现用于将数据存储在存储器矩阵内的地址的读取或写入操作和移位操作，因此获得具有高处理速度的存储器电路。

公开(公告)号：US4562424A

公开(公告)日：1985-12-31

申请号：US517398

申请日：1983-07-26

申请人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Shuichi Torii ,  Kazuyoshi Ogawa

发明人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Shuichi Torii ,  Kazuyoshi Ogawa

IPC分类号： G01R22/00 ,  G01R21/00 ,  G01R21/127 ,  G01R21/133 ,  G06G7/186 ,  G01R21/06

CPC分类号： G01R21/133 ,  G01R21/00

摘要： An integrator circuit comprising reset means by which, when it is detected that an integrator output V.sub.p for an input analog signal coincides with a plus or minus reference value, the integral output is reset to the vicinity of the middle of the plus and minus reference values, in effect, without interrupting the integrating operation; a circuit which produces a pulse each time coincidence is detected; and a circuit which produces a direction signal indicating whether the coincidence results from an increase or a decrease of the integral input.The pulses produced in the state in which the direction signal is indicating an increase are counted up, and the pulses produced in the state in which the direction signal is indicating a decrease are counted down, whereby the precise integral value of the input analog signal can be detected.

摘要翻译： 一种积分器电路，包括复位装置，当检测到输入模拟信号的积分器输出Vp与正或负参考值一致时，积分输出被复位到正和负参考值的中间附近 实际上不中断整合操作; 检测每次产生脉冲的电路; 以及产生指示由积分输入的增加或减少引起的一致性的方向信号的电路。 在方向信号指示增加的状态下产生的脉冲向上计数，并且在方向信号指示减小的状态下产生的脉冲向下计数，由此输入模拟信号的精确积分值 被检测。

公开(公告)号：US4270220A

公开(公告)日：1981-05-26

申请号：US70817

申请日：1979-08-29

申请人： Yoshimune Hagiwara ,  Terumi Sawase ,  Atsushi Takai ,  Yuzo Kita ,  Akira Honda

发明人： Yoshimune Hagiwara ,  Terumi Sawase ,  Atsushi Takai ,  Yuzo Kita ,  Akira Honda

IPC分类号： H03J5/02 ,  H04B1/26

CPC分类号： H03J5/0263

摘要： A television receiver of electronic tuning type employing a variable capacitance diode in a local oscillator of its tuning circuit, which comprises a memory storing a plurality of digital data indicative of tuning voltages corresponding to a plurality of channels respectively so that a tuning voltage corresponding to a selected channel can be applied to the variable capacitance diode in the tuning circuit, a D/A converter converting a digital data corresponding to a selected channel into an analog voltage to be supplied to the variable capacitance diode, and a tuning voltage control circuit which functions to sequentially modify, at a predetermined rate, the digital data of the selected channel read out from the memory until the tuning point is reached in the tuning circuit, and which applies sequentially such a signal to the D/A converter, whereby the tuning circuit can be tuned to the selected channel regardless of secular and other variations in the operating characteristic of the variable capacitance diode.

摘要翻译： 一种在其调谐电路的本地振荡器中采用可变电容二极管的电子调谐型电视接收机，其包括分别存储表示与多个通道对应的调谐电压的多个数字数据的存储器，使得对应于 所选择的通道可以应用于调谐电路中的可变电容二极管，D / A转换器将对应于所选通道的数字数据转换为要提供给可变电容二极管的模拟电压，以及调谐电压控制电路，其功能 以预定速率顺序地修改从存储器读出的所选通道的数字数据，直到在调谐电路中达到调谐点，并且将该信号顺序地施加到D / A转换器，由此调谐电路 可以调谐到所选择的频道，而不管v的操作特性的长期和其他变化 可调电容二极管。

公开(公告)号：US5430885A

公开(公告)日：1995-07-04

申请号：US782760

申请日：1991-10-22

申请人： Kenji Kaneko ,  Hirotada Ueda ,  Tetsuya Nakagawa ,  Atsuchi Kiuchi ,  Yoshimune Hagiwara ,  You Takamori ,  Takanori Toyomasu

发明人： Kenji Kaneko ,  Hirotada Ueda ,  Tetsuya Nakagawa ,  Atsuchi Kiuchi ,  Yoshimune Hagiwara ,  You Takamori ,  Takanori Toyomasu

IPC分类号： G06F15/16 ,  G06F9/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06T1/20

CPC分类号： G06F15/8007 ,  G06F15/17337 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06T1/20

摘要： A multi-processor system for multidimensional image signal processing includes a plurality of co-processors and a host processor which issues processor numbers and a command to the co-processors through a bus. Due to the multi-dimensional nature of the processor numbers, data processing for given ranges of an image signal can be shared by the co-processors. A particular multi-dimensional processor number issued by the host computer which allows simultaneous communication to be performed between the host processor and the co-processors.

摘要翻译： 用于多维图像信号处理的多处理器系统包括多个协处理器和通过总线向处理器发出处理器号码和命令的主机处理器。 由于处理器号码的多维特性，图像信号的给定范围的数据处理可由协处理器共享。 由主计算机发行的特定多维处理器号码，允许在主机处理器和协处理器之间执行同时通信。

公开(公告)号：US5165086A

公开(公告)日：1992-11-17

申请号：US527866

申请日：1990-05-24

申请人： Shigehiro Kamejima ,  Yoshimune Hagiwara ,  Kouki Noguchi ,  Minoru Ishii ,  Tadahiko Nishimukai ,  Hideo Nakamura ,  Haruo Koizumi ,  Hiroyuki Masuda

发明人： Shigehiro Kamejima ,  Yoshimune Hagiwara ,  Kouki Noguchi ,  Minoru Ishii ,  Tadahiko Nishimukai ,  Hideo Nakamura ,  Haruo Koizumi ,  Hiroyuki Masuda

IPC分类号： H01L27/02

CPC分类号： H01L27/0207

摘要： A microprocessor chip including a ROM portion for storing a microprogram, an execution unit portion for executing an arithmetic operation and random logic circuits disposed between the ROM portion and the execution unit portion. Two-level metal lines technology is used for supplying power for grounding and for providing input/output interconnect lines for the random logic circuits.

摘要翻译： 一种微处理器芯片，包括用于存储微程序的ROM部分，用于执行算术运算的执行单元部分和布置在ROM部分和执行单元部分之间的随机逻辑电路。 两级金属线技术用于为接地提供电源，并为随机逻辑电路提供输入/输出互连线。

公开(公告)号：US4752905A

公开(公告)日：1988-06-21

申请号：US795451

申请日：1985-11-06

申请人： Tetsuya Nakagawa ,  Kenji Kaneko ,  Yoshimune Hagiwara ,  Hitoshi Matsushima ,  Hirotada Ueda

发明人： Tetsuya Nakagawa ,  Kenji Kaneko ,  Yoshimune Hagiwara ,  Hitoshi Matsushima ,  Hirotada Ueda

IPC分类号： G06F7/53 ,  G06F7/52 ,  G06F7/533

CPC分类号： G06F7/5318 ,  G06F7/5338

摘要： A high-speed multiplier adapted to VLSI with a regularly arranged structure having a reduced number of addition stages. There is provided a carry save adder circuit wherein a time difference is imparted to signals input to full adders, in order to eliminate extra wait time in the signal propagation. That is, a carry signal of a full adder of two stages over is input with a speed increase of 1/2T.sub.FA.

摘要翻译： 适用于VLSI的高速倍增器，其具有规则排列的结构，其数量减少。 提供了进位保存加法器电路，其中对输入到全加器的信号赋予时间差，以便消除信号传播中的额外等待时间。 也就是说，输入两级的全加器的进位信号，速度增加为1 / 2TFA。

公开(公告)号：US4620292A

公开(公告)日：1986-10-28

申请号：US700908

申请日：1985-02-12

申请人： Yoshimune Hagiwara ,  Shizuo Sugiyama ,  Narimichi Maeda ,  Osamu Yumoto ,  Takashi Akazawa ,  Masahito Kobayashi ,  Yasuhiro Kita ,  Yuzo Kita

发明人： Yoshimune Hagiwara ,  Shizuo Sugiyama ,  Narimichi Maeda ,  Osamu Yumoto ,  Takashi Akazawa ,  Masahito Kobayashi ,  Yasuhiro Kita ,  Yuzo Kita

IPC分类号： G06F7/00 ,  G06F5/01 ,  G06F7/50 ,  G06F7/57 ,  G06F7/76 ,  G06F17/10 ,  H03M7/24

CPC分类号： G06F7/483 ,  G06F5/012 ,  G06F7/485 ,  G06F2207/3856 ,  G06F7/49921

摘要： A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor includes an arithmetic logic unit for floating point data and/or fixed point data in which there is selectively provided a first pair of first and second floating point data which are to be subjected to an arithmetic operation, or a second pair of data consisting of third floating (fixed) point data which is to be converted to fixed (floating) point data and fourth floating point data which is a reference data for the conversion. If the first pair is selected the first and second pair of floating point data are subjected to the arithmetic operation. If the second pair is selected, the conversion of the fixed (floating) point data to floating (fixed) point data is effected by normalizing the third data with the value of the exponent part of the fourth data.

公开(公告)号：US4577154A

公开(公告)日：1986-03-18

申请号：US517407

申请日：1983-07-26

申请人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Kazuyoshi Ogawa ,  Hideo Hara

发明人： Katsuaki Takagi ,  Yuzo Kita ,  Yoshimune Hagiwara ,  Kazuyoshi Ogawa ,  Hideo Hara

IPC分类号： G01R22/00 ,  G01R21/127 ,  G06G7/161 ,  G06G7/186 ,  H03K7/06 ,  H03K7/08 ,  H03M1/50 ,  H03M1/82 ,  H03K5/05

CPC分类号： H03M1/82 ,  H03K7/08

摘要： A pulse width modulation circuit which can cancel the mean error of pulse width modulation with respect to time due to the offset voltage of a triangular wave signal and to the offset voltage of a comparator, by adding simple circuits to an existing pulse width modulation circuit. The invention relates also to an integration circuit of the product of two analog signals using the pulse width modulation circuit described above.The principle of the present invention combines a circuit for cancelling the offset of a triangular wave signal by inverting either the triangular wave signal with respect to an input signal or the input signal with respect to the triangular wave signal, in every predetermined period, with a circuit for eliminating the offset of a comparator by inverting the output of the comparator and replacing the input terminals of the comparator if the input signal is not inverted, or connecting the input terminal of the comparator as such if the input signal is inverted.

摘要翻译： 一种脉冲宽度调制电路，通过将简单的电路加到现有的脉宽调制电路上，可以消除三角波信号的偏移电压和比较器的偏移电压相对于时间的脉冲宽度调制的平均误差。 本发明还涉及使用上述脉冲宽度调制电路的两个模拟信号的乘积的积分电路。 本发明的原理结合了用于消除三角波信号的偏移的电路，通过在每个预定周期内相对于三角波信号相对于输入信号或输入信号反转三角波信号， 电路，用于通过反相比较器的输出来消除比较器的偏移，并且如果输入信号不被反相则替换比较器的输入端，或者如果输入信号反相则连接比较器的输入端。

公开(公告)号：US5511211A

公开(公告)日：1996-04-23

申请号：US102156

申请日：1993-08-04

申请人： Yasushi Akao ,  Shiro Baba ,  Terumi Sawase ,  Yoshimune Hagiwara

发明人： Yasushi Akao ,  Shiro Baba ,  Terumi Sawase ,  Yoshimune Hagiwara

IPC分类号： G06F9/24 ,  G06F9/445 ,  G06F15/78 ,  G06F9/312 ,  G06F13/40 ,  G06F15/20

CPC分类号： G06F8/60 ,  G06F15/7814 ,  G06F9/24

摘要： In developing the function of a data processing system using a semiconductor integrated circuit for data processing, comprising a non-volatile logical function block to which data is written electrically and a logical operation block utilizing the logical function block to execute the logic operation, data corresponding to the required specification and function of the system is written in the logical function block. Thereby, flexibility is obtained for setting and changing the required function to the semiconductor integrated circuit. The semiconductor integrated circuit also has an operation specification written to the logical block by a writing device designed to write to a non-volatile semiconductor storage device thereby improving the convenience of setting the functions required of the semiconductor integrated circuit.

摘要翻译： 在开发使用半导体集成电路进行数据处理的数据处理系统的功能中，包括电子地写入数据的非易失性逻辑功能块和利用逻辑功能块执行逻辑运算的逻辑运算块，对应的数据 将系统的所需规格和功能写入逻辑功能块。 由此，可以获得将半导体集成电路所需的功能设定和变更的灵活性。 半导体集成电路还具有通过设计成写入非易失性半导体存储装置的写入装置写入逻辑块的操作规范，从而提高了设置半导体集成电路所需功能的便利性。