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    STI stress modification by nitrogen plasma treatment for improving performance in small width devices
    12.
    发明授权
    STI stress modification by nitrogen plasma treatment for improving performance in small width devices 失效
    通过氮等离子体处理进行STI应力改进，以改善小宽度器件的性能

    公开(公告)号：US06887798B2

    公开(公告)日：2005-05-03

    申请号：US10250047

    申请日：2003-05-30

    申请人： Sadanand V. Deshpande ,  Bruce B. Doris ,  Werner A. Rausch ,  James A. Slinkman

    发明人： Sadanand V. Deshpande ,  Bruce B. Doris ,  Werner A. Rausch ,  James A. Slinkman

    IPC分类号： H01L21/318 ,  H01L21/762 ,  H01L29/10 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L29/7842 ,  H01L21/3185 ,  H01L21/76237 ,  H01L29/1033

    摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

    摘要翻译： 一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。 氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。 在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。 在另一个实施例中，等离子体氮化处理发生在沟槽填充之后。 在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。 该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。

    Method for efficiently determining a fermi-dirac integrals
    14.
    发明授权
    Method for efficiently determining a fermi-dirac integrals 失效
    有效确定费米尔 - 迪拉克积分的方法

    公开(公告)号：US6101519A

    公开(公告)日：2000-08-08

    申请号：US98909

    申请日：1998-06-17

    申请人： James A. Slinkman

    发明人： James A. Slinkman

    IPC分类号： G06F17/10 ,  G06F7/38

    CPC分类号： G06F17/10

    摘要： A computer implemented method for efficiently evaluating a Fourier sine/cosine transform of a bounded analytical function is described. The transform is computed in a plurality of steps which reduces the required transform to a sum of two terms which can be efficiently evaluated using a digital computer. The computer evaluates the first and second terms as definite integrals. The first integral is evaluated via standard techniques, and the second integral is evaluated as a definite integral of a sum of terms which converges. The method is advantageously used to provide a model of semiconductor devices which takes into account quantum mechanical effects while minimizing compute operation time. A look-up table of semiconductor carrier density versus spatially dependent field values can optionally be constructed.

    摘要翻译： 描述了一种用于有效评估有界分析函数的傅里叶正弦/余弦变换的计算机实现方法。 在多个步骤中计算变换，其将所需变换减少到可以使用数字计算机有效评估的两个项的和。 计算机将第一和第二项评估为定积分。 第一个积分通过标准技术进行评估，第二个积分被评估为收敛的项的总和的一个积分。 该方法有利地用于提供在最小化计算操作时间的同时考虑量子力学效应的半导体器件的模型。 可以可选地构建半导体载流子密度与空间依赖场值的查找表。

    Optimized Device Isolation
    16.
    发明申请
    Optimized Device Isolation 有权
    优化设备隔离

    公开(公告)号：US20100117122A1

    公开(公告)日：2010-05-13

    申请号：US12269073

    申请日：2008-11-12

    申请人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St Onge ,  James A. Slinkman

    发明人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St Onge ,  James A. Slinkman

    IPC分类号： H01L27/092 ,  H01L27/085

    CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928

    摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.

    摘要翻译： 用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。 该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。 一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域上方，并在所有p阱区域下方， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。 隔离MOSFET的n阱连接到深n波段区域。 所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

    STI stress modification by nitrogen plasma treatment for improving performance in small width devices
    17.
    发明授权
    STI stress modification by nitrogen plasma treatment for improving performance in small width devices 有权
    通过氮等离子体处理进行STI应力改进，以改善小宽度器件的性能

    公开(公告)号：US07479688B2

    公开(公告)日：2009-01-20

    申请号：US10751831

    申请日：2004-01-05

    申请人： Sadanand V. Deshpande ,  Bruce B. Doris ,  Werner A. Rausch ,  James A. Slinkman

    发明人： Sadanand V. Deshpande ,  Bruce B. Doris ,  Werner A. Rausch ,  James A. Slinkman

    IPC分类号： H01L29/72

    CPC分类号： H01L29/7842 ,  H01L21/3185 ,  H01L21/76237 ,  H01L29/1033

    摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.

    摘要翻译： 一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。 氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。 在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。 在又一实施例中，等离子体氮化处理发生在沟槽填充之后。 在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。 该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。

    METHOD FOR ADJUSTING LITHOGRAPHIC MASK FLATNESS USING THERMALLY INDUCED PELLICLE STRESS
    19.
    发明申请
    METHOD FOR ADJUSTING LITHOGRAPHIC MASK FLATNESS USING THERMALLY INDUCED PELLICLE STRESS 有权
    使用热诱导油脂应力调整光刻掩模的方法

    公开(公告)号：US20080131795A1

    公开(公告)日：2008-06-05

    申请号：US12029506

    申请日：2008-02-12

    申请人： Emily F. Gallagher ,  Louis M. Kindt ,  James A. Slinkman ,  Richard E. Wistron

    发明人： Emily F. Gallagher ,  Louis M. Kindt ,  James A. Slinkman ,  Richard E. Wistron

    IPC分类号： G03F1/00

    CPC分类号： G03F1/64 ,  G03F1/60

    摘要： A method for adjusting the flatness of a lithographic mask includes determining an initial mask flatness of the mask, determining an applied stress for bringing the mask to a desired mask flatness, and determining a mounting temperature of a pellicle frame to be mounted to the mask, the mounting temperature corresponding to the applied stress. The actual temperature of the pellicle frame is adjusted to the determined mounting temperature, and the pellicle frame is mounted to the mask at the mounting temperature.

    摘要翻译： 调整光刻掩模的平坦度的方法包括：确定掩模的初始掩模平坦度，确定施加的应力以使掩模达到期望的掩模平坦度，以及确定要安装到掩模的防护薄膜组件框架的安装温度， 安装温度对应于施加的应力。 防护薄膜组件框架的实际温度被调整到确定的安装温度，并且防护膜框架在安装温度下安装到掩模上。