公开(公告)号：US20050265114A1

公开(公告)日：2005-12-01

申请号：US11197588

申请日：2005-08-05

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

IPC分类号： G11C16/02 ,  G11C8/02 ,  G11C16/12

CPC分类号： G11C16/3459 ,  G11C16/12 ,  G11C2216/14

摘要： Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic “1” (or logic “0”), writing operation to bits corresponding to write data having the logic “0” (or logic “1) is successively performed.

摘要翻译： 公开了一种具有缩短的总写入时间的非易失性存储器，能够通过使写入电流恒定而稳定地写入数据，同时减少由升压电路产生的电压的波动。 在诸如闪速存储器的非易失性存储器中，在写入操作时确定数据。 在跳过对应于具有逻辑“1”（或逻辑“0”）的写入数据的位时，对与具有逻辑“0”（或逻辑“1”的写入数据相对应的位进行写操作）。

公开(公告)号：US06477090B2

公开(公告)日：2002-11-05

申请号：US09939708

申请日：2001-08-28

申请人： Takashi Yamaki ,  Kan Takeuchi ,  Mitsuru Hiraki ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masamichi Fujito

发明人： Takashi Yamaki ,  Kan Takeuchi ,  Mitsuru Hiraki ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masamichi Fujito

IPC分类号： G11C700

CPC分类号： G11C29/50008 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/28 ,  G11C16/30 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.

摘要翻译： 提供一种其特性对于其所需特性需要实现而不受设备特性不均匀影响的电路高度可靠地调节的半导体器件。 提供连接到外部测量端子的用于安培数测量的复制MOS晶体管。 要实现其期望特性的延迟电路和其它电路具有与复制MOS晶体管相同的工艺形成的恒流源MOS晶体管，并且微调电压vtri通常施加到恒流源MOS晶体管的各个栅极 和复制MOS晶体管。 基于从外部测量终端测量的电流强度确定的修整数据被存储到诸如电可重写非易失性存储器等的存储装置中。 修整数据确定修整电压vtri。

公开(公告)号：US07190615B2

公开(公告)日：2007-03-13

申请号：US10810672

申请日：2004-03-29

申请人： Masamichi Fujito ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Ayako Kakuda ,  Akira Kato ,  Toshihiro Tanaka

发明人： Masamichi Fujito ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Ayako Kakuda ,  Akira Kato ,  Toshihiro Tanaka

IPC分类号： G11C11/34 ,  G11C5/06

CPC分类号： G11C7/18 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  G11C2207/005 ,  G11C2216/22

摘要： The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.

摘要翻译： 能够进行电气重写的片上非易失性存储器的读取速度增加。 非易失性存储器具有分层位线结构，其具有对多个存储器阵列中的每一个特定的第一位线，在多个存储器阵列之间共享的第二位线，第一选择器电路，用于为每个存储器阵列选择第一位线 将所选择的第一位线连接到第二位线，以及布置在第一选择器电路的输出和第二位线之间的感测放大器。 具有划分的存储器阵列的层次位线结构可以减小感测放大器的输入负载能力。

公开(公告)号：US6122196A

公开(公告)日：2000-09-19

申请号：US219435

申请日：1998-12-23

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/24 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/24 ,  G11C16/30

摘要： The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.

摘要翻译： 本发明提出了一种非易失性半导体存储器，包括多个主位线，连接到主位线的多个子位线以及多个存储单元阵列，每个存储单元阵列包括多个非易失性半导体存储器 细胞排列成阵列。 这些存储单元中的每一个具有源极端子，漏极端子和控制栅极，并且每个源极 - 漏极路径连接到子位线。 在主位线和连接到主位线的子位线之间设置第一晶体管的源极 - 漏极路径，并且第二晶体管的源极 - 漏极路径连接到子位线。

公开(公告)号：US07072218B2

公开(公告)日：2006-07-04

申请号：US10486638

申请日：2002-07-03

申请人： Masamichi Fujito ,  Yuko Nakamura ,  Kazufumi Suzukawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa

发明人： Masamichi Fujito ,  Yuko Nakamura ,  Kazufumi Suzukawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa

IPC分类号： G11C16/04

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/08 ,  G11C16/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high voltage output driver derives operational power from high voltages and a switching circuit which reverses the output state of the high voltage output driver. The high voltage output driver has in a current path of the high voltages, a series circuit of a first MOS transistor (M1) and second MOS transistor (M2), with the serial connection node thereof being the driver output terminal. The switching circuit operates to reverse the complementary switching states of the first and second MOS transistors such that one transistor in the on-state is switched to an off-state first and the other transistor is switched to an on-state afterward. Even if the other MOS transistor has its Vds exceeding the minimum breakdown voltage when it operates to turn on, the through current path is already shut off, and therefore the high voltage output driver does not break down.

摘要翻译： 高电压输出驱动器从高电压导出工作电源，并切换反向高压输出驱动器的输出状态的开关电路。 高压输出驱动器具有高电压的电流路径，第一MOS晶体管（M 1）和第二MOS晶体管（M 2）的串联电路，其串联连接节点是驱动器输出端子。 开关电路操作以反转第一和第二MOS晶体管的互补开关状态，使得处于导通状态的一个晶体管首先被切换到截止状态，而另一个晶体管之后被切换到导通状态。 即使其他MOS晶体管的Vds在其操作导通时其Vds超过最小击穿电压，直通电流路径已被切断，因此高压输出驱动器不会分解。

公开(公告)号：US20070153618A1

公开(公告)日：2007-07-05

申请号：US11713039

申请日：2007-03-02

申请人： Masamichi Fujito ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Ayako Kakuda ,  Akira Kato ,  Toshihiro Tanaka

发明人： Masamichi Fujito ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Ayako Kakuda ,  Akira Kato ,  Toshihiro Tanaka

IPC分类号： G11C8/00

CPC分类号： G11C7/18 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  G11C2207/005 ,  G11C2216/22

摘要： The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.

公开(公告)号：US06307780B1

公开(公告)日：2001-10-23

申请号：US09627411

申请日：2000-07-27

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

IPC分类号： G11C700

CPC分类号： G11C16/0416 ,  G11C16/24 ,  G11C16/30

摘要： The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.

摘要翻译： 本发明提出了一种非易失性半导体存储器，包括多个主位线，连接到主位线的多个子位线以及多个存储单元阵列，每个存储单元阵列包括多个非易失性半导体存储器 细胞排列成阵列。 这些存储单元中的每一个具有源极端子，漏极端子和控制栅极，并且每个源极 - 漏极路径连接到子位线。 在主位线和连接到主位线的子位线之间设置第一晶体管的源极 - 漏极路径，并且第二晶体管的源极 - 漏极路径连接到子位线。

公开(公告)号：US07342826B2

公开(公告)日：2008-03-11

申请号：US11713039

申请日：2007-03-02

申请人： Masamichi Fujito ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Ayako Kakuda ,  Akira Kato ,  Toshihiro Tanaka

发明人： Masamichi Fujito ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Ayako Kakuda ,  Akira Kato ,  Toshihiro Tanaka

IPC分类号： G11C11/34 ,  G11C5/06

CPC分类号： G11C7/18 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C16/30 ,  G11C2207/005 ,  G11C2216/22

摘要： The read speed of an on-chip nonvolatile memory enabling electric rewrite is increased. The nonvolatile memory has a hierarchal bit line structure having first bit lines specific to each of a plurality of memory arrays, a second bit line shared between the plurality of memory arrays, a first selector circuit selecting the first bit line for each of the memory arrays to connect the selected first bit line to the second bit line, and a sense amp arranged between the output of the first selector circuit and the second bit line. The hierarchal bit line structure having the divided memory arrays can reduce the input load capacity of the sense amp.

摘要翻译： 能够进行电气重写的片上非易失性存储器的读取速度增加。 非易失性存储器具有分层位线结构，其具有对多个存储器阵列中的每一个特定的第一位线，在多个存储器阵列之间共享的第二位线，第一选择器电路，用于为每个存储器阵列选择第一位线 将所选择的第一位线连接到第二位线，以及布置在第一选择器电路的输出和第二位线之间的感测放大器。 具有划分的存储器阵列的层次位线结构可以减小感测放大器的输入负载能力。

公开(公告)号：US06480418B2

公开(公告)日：2002-11-12

申请号：US09951979

申请日：2001-09-14

申请人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

发明人： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazuyoshi Shiba ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takayuki Oshima ,  Sonoko Abe ,  Kiyoshi Matsubara

IPC分类号： G11C1604

CPC分类号： G11C16/0416 ,  G11C16/24 ,  G11C16/30

摘要： The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.

摘要翻译： 本发明提出了一种非易失性半导体存储器，包括多个主位线，连接到主位线的多个子位线以及多个存储单元阵列，每个存储单元阵列包括多个非易失性半导体存储器 细胞排列成阵列。 这些存储单元中的每一个具有源极端子，漏极端子和控制栅极，并且每个源极 - 漏极路径连接到子位线。 在主位线和连接到主位线的子位线之间设置第一晶体管的源极 - 漏极路径，并且第二晶体管的源极 - 漏极路径连接到子位线。

公开(公告)号：US06542411B2

公开(公告)日：2003-04-01

申请号：US09970675

申请日：2001-10-05

申请人： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Yoshiki Kawajiri ,  Masamichi Fujito

发明人： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Yoshiki Kawajiri ,  Masamichi Fujito

IPC分类号： G11C1604

CPC分类号： G11C16/3472 ,  G11C16/30 ,  G11C16/3468 ,  G11C16/3481

摘要： A nonvolatile memory includes a control register (CRG) for providing instructions as to basic operations such as writing, erasing, reading, etc., a boosted voltage attainment detecting circuit for detecting whether a voltage boosted by a booster circuit has reached a desired level, a circuit which counts the time required to apply each of write and erase voltages, and a circuit which detects the completion of the writing or erasing. Respective operations are automatically advanced by simple setting of the operation instructions to the control register. After the completion of the operations, an end flag (FLAG) provided within the control register is set to notify the completion of the writing or erasing.

摘要翻译： 非易失性存储器包括用于提供关于基本操作（诸如写入，擦除，读取等）的指令的控制寄存器（CRG），用于检测由升压电路升压的电压是否达到期望水平的升压电压达到检测电路， 计算施加写入和擦除电压中的每一个所需的时间的电路，以及检测写入或擦除完成的电路。 通过将操作指令简单设置到控制寄存器，可以自动提高各自的操作。 操作完成后，设置控制寄存器内提供的结束标志（FLAG），通知写入或擦除完成。