公开(公告)号：US08928126B2

公开(公告)日：2015-01-06

申请号：US13670476

申请日：2012-11-07

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Chin-Cheng Chien

IPC: H01L21/02

CPC classification number: H01L21/0262 ,  H01L21/0237 ,  H01L21/02576 ,  H01L21/02639 ,  H01L29/0843 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

Abstract: A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer.

Abstract translation: 形成外延层的方法包括以下步骤。 首先，执行第一外延生长工艺以在衬底上形成第一外延层，并且在第一外延期间引入硅气体源，碳气体源，磷气体源和锗气体源 生长工艺以形成包括硅，碳，磷和锗的第一外延层。 随后，进行第二外延生长工艺以形成第二外延层，并且第二外延层中的多个元件小于第一外延层中的元件的数量。

公开(公告)号：US08927376B2

公开(公告)日：2015-01-06

申请号：US14260294

申请日：2014-04-24

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Teng-Chun Hsuan ,  Chin-Cheng Chien

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate. Preferably, the semiconductor substrate includes at least a recess, the undoped first epitaxial layer has a lattice constant, a bottom thickness, and a side thickness, in which the lattice constant is different from a lattice constant of the semiconductor substrate and the bottom thickness is substantially larger than or equal to the side thickness.

Abstract translation: 公开了一种用于形成外延层的方法。 该方法包括提供半导体衬底以及在半导体衬底中形成未掺杂的第一外延层的步骤。 优选地，半导体衬底至少包括凹部，未掺杂的第一外延层具有晶格常数，底部厚度和侧面厚度，其中晶格常数不同于半导体衬底的晶格常数，底部厚度为 基本上大于或等于侧厚度。

公开(公告)号：US20130256701A1

公开(公告)日：2013-10-03

申请号：US13905148

申请日：2013-05-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract translation: 应变硅沟道半导体结构包括具有上表面的衬底，形成在上表面上的栅极结构，在栅极结构的侧面处形成在衬底中的至少一个凹部，其中凹部具有至少一个侧壁，其具有 上侧壁和下侧壁在与栅极结构的方向上凹陷，并且上侧壁和水平面之间的夹角在54.5°-90°之间，并且填充到两个凹部中的外延层。

公开(公告)号：US20150255576A1

公开(公告)日：2015-09-10

申请号：US14201373

申请日：2014-03-07

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Sheng-Hsu Liu

IPC: H01L29/66 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/02521 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device is described. A spacer is formed on a sidewall of a fin structure. A portion of the fin structure is removed to form a cavity exposing at least a portion of the inner sidewall of the spacer. An epitaxy process is performed based on the remaining fin structure to form a semiconductor layer that has a shovel-shaped cross section including: a stem portion in the cavity, and a shovel plane portion contiguous with the stem portion. A semiconductor device is also described, which includes the spacer, the remaining fin structure and the semiconductor layer that are mentioned above.

Abstract translation: 对半导体装置的制造方法进行说明。 间隔件形成在翅片结构的侧壁上。 翼片结构的一部分被去除以形成暴露间隔物的内侧壁的至少一部分的空腔。 基于剩余的翅片结构进行外延工艺以形成具有铲形截面的半导体层，该半导体层包括：腔体中的杆部分和与杆部分相邻的铲平面部分。 还描述了一种半导体器件，其包括上述的间隔物，剩余的鳍结构和半导体层。

公开(公告)号：US09070635B2

公开(公告)日：2015-06-30

申请号：US13963688

申请日：2013-08-09

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Yu-Cheng Tung

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/02046 ,  H01L21/02057 ,  H01L21/76224 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A removing method including the following steps. A substrate is transferred into an etching machine, wherein the substrate has a material layer formed thereon. A cycle process is performed. The cycle process includes performing an etching process to remove a portion of the material layer, and performing an annealing process to remove a by-product generated by the etching process. The cycle process is repeated at least one time. The substrate is transferred out of the etching machine. In the removing method of the invention, the cycle process is performed multiple times to effectively remove the undesired thickness of the material layer and reduce the loading effect.

Abstract translation: 一种移除方法，包括以下步骤。 将衬底转移到蚀刻机中，其中衬底具有形成在其上的材料层。 执行循环过程。 循环过程包括执行蚀刻工艺以去除材料层的一部分，以及执行退火处理以除去由蚀刻工艺产生的副产物。 循环过程至少重复一次。 将基板转移出蚀刻机。 在本发明的除去方法中，进行多次循环处理以有效地去除材料层的不希望的厚度并降低负载效果。

公开(公告)号：US08999793B2

公开(公告)日：2015-04-07

申请号：US14306250

申请日：2014-06-17

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/1054 ,  H01L29/66484 ,  H01L29/785

Abstract: A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor.

Abstract translation: 多栅极场效应晶体管包括鳍状结构，栅极结构，至少外延结构和梯度盖层。 鳍状结构位于基板上。 栅极结构设置在鳍状结构和衬底的一部分上。 外延结构位于栅极结构旁边的鳍状结构上。 梯度盖层位于每个外延结构上。 梯度盖层是化合物半导体，化合物半导体的成分之一的浓度具有从内向外减小的梯度分布。 此外，本发明还提供一种形成所述多栅极场效应晶体管的多栅极场效应晶体管工艺。

公开(公告)号：US20150044879A1

公开(公告)日：2015-02-12

申请号：US13963688

申请日：2013-08-09

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Yu-Cheng Tung

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01L21/02046 ,  H01L21/02057 ,  H01L21/76224 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A removing method including the following steps. A substrate is transferred into an etching machine, wherein the substrate has a material layer formed thereon. A cycle process is performed. The cycle process includes performing an etching process to remove a portion of the material layer, and performing an annealing process to remove a by-product generated by the etching process. The cycle process is repeated at least one time. The substrate is transferred out of the etching machine. In the removing method of the invention, the cycle process is performed multiple times to effectively remove the undesired thickness of the material layer and reduce the loading effect.

Abstract translation: 一种移除方法，包括以下步骤。 将衬底转移到蚀刻机中，其中衬底具有形成在其上的材料层。 执行循环过程。 循环过程包括执行蚀刻工艺以去除材料层的一部分，以及执行退火工艺以除去由蚀刻工艺产生的副产物。 循环过程至少重复一次。 将基板转移出蚀刻机。 在本发明的除去方法中，进行多次循环处理以有效地去除材料层的不希望的厚度并降低负载效果。

公开(公告)号：US08884346B2

公开(公告)日：2014-11-11

申请号：US14156442

申请日：2014-01-15

Applicant: United Microelectronics Corp.

Inventor： Chin-I Liao ,  Chin-Cheng Chien

IPC: H01L29/786 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/66628 ,  H01L29/66636

Abstract: A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.

Abstract translation: 半导体结构包括栅极结构，外延层和含碳硅锗覆盖层。 栅极结构位于衬底上。 外延层位于栅极结构旁边的衬底中。 含碳硅锗覆盖层位于外延层上。 否则，还提供了用于形成所述半导体结构的半导体工艺。

公开(公告)号：US08853740B2

公开(公告)日：2014-10-07

申请号：US13905148

申请日：2013-05-30

Applicant: United Microelectronics Corp.

Inventor： Chan-Lon Yang ,  Ted Ming-Lang Guo ,  Chin-I Liao ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7848 ,  H01L21/30608 ,  H01L21/3247 ,  H01L21/823425 ,  H01L29/6656 ,  H01L29/66636

Abstract: A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses.

Abstract translation: 应变硅沟道半导体结构包括具有上表面的衬底，形成在上表面上的栅极结构，在栅极结构的侧面处形成在衬底中的至少一个凹部，其中凹部具有至少一个侧壁，其具有 上侧壁和下侧壁在与栅极结构的方向上凹陷，并且上侧壁和水平面之间的夹角在54.5°-90°之间，并且填充到两个凹部中的外延层。

公开(公告)号：US20140191285A1

公开(公告)日：2014-07-10

申请号：US14203581

申请日：2014-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-I Liao ,  Teng-Chun Hsuan ,  I-Ming Lai ,  Chin-Cheng Chien

IPC: H01L29/165

CPC classification number: H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant. The epitaxial structures and the undoped cap layer include a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant. The second lattice constant is larger than the first lattice constant. The second semiconductor material in the epitaxial structure includes a first concentration and the second semiconductor material in the undoped cap layer includes a second concentration. The second concentration is lower than the first concentration, and is upwardly decreased.

Abstract translation: 具有外延结构的半导体器件包括位于衬底上的栅极结构，在栅极结构的两侧形成在衬底中的外延结构，以及形成在外延结构上的未掺杂的帽层。 外延结构包括掺杂剂。 外延结构和未掺杂的帽层包括具有第一晶格常数的第一半导体材料和具有第二晶格常数的第二半导体材料。 第二晶格常数大于第一晶格常数。 外延结构中的第二半导体材料包括第一浓度，未掺杂帽层中的第二半导体材料包括第二浓度。 第二浓度低于第一浓度，并且向上减少。