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公开(公告)号：US08912074B2
公开(公告)日：2014-12-16
申请号：US14329982
申请日：2014-07-13
Applicant: United Microelectronics Corp.
Inventor： En-Chiuan Liou , Po-Chao Tsao , Chia-Jui Liang , Jia-Rong Wu
IPC: H01L21/76 , H01L21/762
CPC classification number: H01L29/0653 , H01L21/76224 , H01L21/76235 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649
Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.
Abstract translation: 一种形成浅沟槽隔离结构的方法，包括以下步骤：在衬底中形成沟槽，填充沟槽下部的第一绝缘层并在沟槽的上部限定凹陷，在侧壁上形成缓冲层 在凹部中填充第二绝缘层，并执行蒸汽退火处理，以将围绕第一绝缘层的基板转变为氧化物层。
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公开(公告)号：US20140322891A1
公开(公告)日：2014-10-30
申请号：US14329982
申请日：2014-07-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： En-Chiuan Liou , Po-Chao Tsao , Chia-Jui Liang , Jia-Rong Wu
IPC: H01L21/762
CPC classification number: H01L29/0653 , H01L21/76224 , H01L21/76235 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649
Abstract: A method of forming shallow trench isolation structures including the steps of forming a trench in a substrate, filling a first insulating layer in the lower portion of the trench and defining a recess at the upper portion of the trench, forming a buffer layer on the sidewall of the recess, filling a second insulating layer in the recess, and performing a steam annealing process to transform the substrate surrounding the first insulating layer into an oxide layer.
Abstract translation: 一种形成浅沟槽隔离结构的方法，包括以下步骤：在衬底中形成沟槽，填充沟槽下部的第一绝缘层并在沟槽的上部限定凹陷，在侧壁上形成缓冲层 在凹部中填充第二绝缘层，并执行蒸汽退火处理，以将围绕第一绝缘层的基板转变为氧化物层。
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公开(公告)号：US08823132B2
公开(公告)日：2014-09-02
申请号：US13736082
申请日：2013-01-08
Applicant: United Microelectronics Corp.
Inventor： En-Chiuan Liou , Po-Chao Tsao , Chia-Jui Liang , Jia-Rong Wu
IPC: H01L29/00
CPC classification number: H01L29/0653 , H01L21/76224 , H01L21/76235 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649
Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.
Abstract translation: 提供浅沟槽隔离（STI）及其形成方法。 STI结构包括上绝缘部分和下绝缘部分，其中下绝缘部分包括第一绝缘体和围绕第一绝缘体的绝缘层，上绝缘部分包括第二绝缘体和围绕第二绝缘体的缓冲层。 缓冲层的一部分在第一绝缘体和第二绝缘体之间接合，缓冲层的外侧壁和第一绝缘体的侧壁平整。
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公开(公告)号：US20250087559A1
公开(公告)日：2025-03-13
申请号：US18381630
申请日：2023-10-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , I-Fan Chang , Jia-Rong Wu
IPC: H01L23/48 , H01L21/768 , H01L23/532 , H01L23/58
Abstract: A TSV structure includes a substrate. A through via penetrates the substrate. A copper layer fills the through via. A trench is embedded in the substrate and surrounds the copper layer, and a material layer fills the trench. The material layer includes W, Cr, Ir, Re, Zr, SiOC glass, hydrogen-containing silicon oxynitride, silicon oxide or spin-on glass.
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公开(公告)号：US20250078891A1
公开(公告)日：2025-03-06
申请号：US18950204
申请日：2024-11-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Jia-Rong Wu , Yi-Ting Wu
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.
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Patent Agency Ranking
公开(公告)号：US20240203471A1
公开(公告)日：2024-06-20
申请号：US18108025
申请日：2023-02-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Jia-Rong Wu , Yi-Ting Wu
CPC classification number: G11C11/161 , G11C11/1673 , G11C11/1675 , H10B61/20 , H10N50/10
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region, a first gate pattern extending from the first cell region to the third cell region along a first direction, a first diffusion region extending from the first cell region to the second cell region along a second direction, a first metal pattern adjacent to one side of the first gate pattern and overlapping the first diffusion region, a source line pattern extending from the first cell region to the second cell region along the second direction, and a first spin orbit torque (SOT) pattern extending along the first direction and overlapping the first metal pattern and the source line pattern.
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公开(公告)号：US20230282261A1
公开(公告)日：2023-09-07
申请号：US17707934
申请日：2022-03-29
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun-Yen Tseng , Yu-Tse Kuo , Shu-Ru Wang , Jen-Yu Wang , Li-Ping Huang , Yi-Ting Wu , Jia-Rong Wu , Chun-Hsien Huang
CPC classification number: G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675 , H01L27/228 , H01L43/02 , H01L43/08
Abstract: The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.
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公开(公告)号：US20230247914A1
公开(公告)日：2023-08-03
申请号：US18132989
申请日：2023-04-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , I-Fan Chang , Ya-Huei Tsai , Yu-Ping Wang
Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape.
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公开(公告)号：US20210151664A1
公开(公告)日：2021-05-20
申请号：US16702576
申请日：2019-12-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , Ya-Huei Tsai , I-Fan Chang , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack along a first direction; and performing a second patterning process to remove the MTJ stack along a second direction to form MTJs on the substrate.
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公开(公告)号：US09859170B2
公开(公告)日：2018-01-02
申请号：US15434067
申请日：2017-02-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Wei-Cyuan Lo , Ming-Jui Chen , Chia-Lin Lu , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Yi-Kuan Wu , Chih-Sen Huang , Yi-Wei Chen , Tan-Ya Yin , Chia-Wei Huang , Shu-Ru Wang , Yung-Feng Cheng
IPC: H01L21/8238 , H01L21/768 , H01L27/11 , H01L23/535 , H01L27/092 , H01L29/78
CPC classification number: H01L21/823871 , H01L21/31144 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L21/823821 , H01L23/485 , H01L23/535 , H01L27/0922 , H01L27/1104 , H01L27/1108 , H01L29/7851 , H01L29/7853
Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.
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