公开(公告)号：US09362125B2

公开(公告)日：2016-06-07

申请号：US14454332

申请日：2014-08-07

Applicant: United Microelectronics Corp.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Zhen Chen ,  Wei Ta ,  Wei-Chang Liu

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract translation: 描述半导体工艺。 提供具有存储区域，第一设备区域和第二设备区域的半导体衬底。 图案化的电荷捕获层形成在衬底上，覆盖存储区域和第二器件区域，但暴露第一器件区域。 第一栅极氧化物层形成在第一器件区域中。 去除第二装置区域中的电荷捕获层。 第二栅极氧化层形成在第二器件区域中。

公开(公告)号：US20150206894A1

公开(公告)日：2015-07-23

申请号：US14158875

申请日：2014-01-20

Applicant: United Microelectronics Corp.

Inventor： Zhen Chen ,  Shen-De Wang ,  Yi-Shan Chiu ,  Wei Cheng

IPC: H01L27/115 ,  H01L23/00

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11524

Abstract: A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.

Abstract translation: 用于存储器件的布局结构包括多个第一栅极图案，多个第一着陆焊盘图案，多个虚设图案，多个第二着陆焊盘图案和多个第二栅极图案。 第一着陆焊盘图案彼此平行并电连接到第一栅极图案。 交替布置虚拟图案和第一着陆焊盘图案，并且第二着陆焊盘图案分别位于一个第一着陆焊盘图案和一个虚设图案之间。 第二栅极图案电连接到第二着陆焊盘图案。

公开(公告)号：US10699958B2

公开(公告)日：2020-06-30

申请号：US16116730

申请日：2018-08-29

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Ling-Gang Fang ,  Shang Xue

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8239

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

公开(公告)号：US20170338239A1

公开(公告)日：2017-11-23

申请号：US15161419

申请日：2016-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Wang Xiang ,  Yi-Shan Chiu

IPC: H01L27/11582 ,  H01L29/66

CPC classification number: H01L27/1157 ,  H01L29/40117 ,  H01L29/4234

Abstract: A semiconductor structure includes a substrate and a plurality of memory cells disposed on the substrate. Each memory cell includes a gate structure. The gate structures are spaced from each other by a spacing S. Each gate structure includes a dielectric layer and a gate electrode. The dielectric layer has an U-shape and defines an opening toward upside. The gate electrode is disposed in the opening. Each gate structure has a length L. A ratio of S/L is smaller than 1.

公开(公告)号：US09660106B2

公开(公告)日：2017-05-23

申请号：US14462550

申请日：2014-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

公开(公告)号：US20160042957A1

公开(公告)日：2016-02-11

申请号：US14454332

申请日：2014-08-07

Applicant: United Microelectronics Corp.

Inventor： Yuan-Hsiang Chang ,  Yi-Shan Chiu ,  Zhen Chen ,  Wei Ta ,  Wei-Chang Liu

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L21/28282 ,  H01L27/11563 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.

Abstract translation: 描述半导体工艺。 提供具有存储区域，第一设备区域和第二设备区域的半导体衬底。 图案化的电荷捕获层形成在衬底上，覆盖存储区域和第二器件区域，但暴露第一器件区域。 第一栅极氧化物层形成在第一器件区域中。 去除第二装置区域中的电荷捕获层。 第二栅极氧化层形成在第二器件区域中。