公开(公告)号：US09978666B2

公开(公告)日：2018-05-22

申请号：US15663679

申请日：2017-07-28

Applicant: United Microelectronics Corp.

Inventor： Kuei-Sheng Wu ,  Ming-Tse Lin

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/02372 ,  H01L2225/06541

Abstract: A method for is used for forming a semiconductor device. The method includes forming an ILD layer on a substrate and a buffer layer on the ILD layer, wherein at least one contact is formed in the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.

公开(公告)号：US20170221796A1

公开(公告)日：2017-08-03

申请号：US15011433

申请日：2016-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Ming-Tse Lin ,  Kuei-Sheng Wu

IPC: H01L23/48 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A TSV structure includes a substrate comprising at least a TSV opening formed therein, a conductive layer disposed in the TSV opening, and a bi-layered liner disposed in between the substrate and the conductive layer. More important, the bi-layered liner includes a first liner and a second liner, and a Young's modulus of the first liner is different from a Young's modulus of the second liner.

公开(公告)号：US20170186668A1

公开(公告)日：2017-06-29

申请号：US14982565

申请日：2015-12-29

Applicant: United Microelectronics Corp.

Inventor： Kuei-Sheng Wu ,  Ming-Tse Lin

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/02372 ,  H01L2225/06541

Abstract: A method for is used for forming a semiconductor device having a through-substrate via. The method includes providing a preliminary structure having an ILD layer on a substrate and a buffer layer on the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.

公开(公告)号：US20150332996A1

公开(公告)日：2015-11-19

申请号：US14280680

申请日：2014-05-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Kuei-Sheng Wu ,  Ming-Tse Lin ,  Chung-Sung Chiang

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  G03F7/20

CPC classification number: H01L21/486 ,  G03F7/203 ,  G03F7/38 ,  G03F7/70 ,  H01L21/48 ,  H01L21/4846 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/065 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1701 ,  H05K3/0082 ,  H05K2201/10378

Abstract: The present invention provides an interposer including multiple circuit designs and an uppermost circuit design disposed on the circuit designs. A maximum exposure region is defined as a maximum size which can be defined by a single shot of a lithographic scanner. The sizes of the circuit designs below the uppermost circuit design are smaller than the size of the maximum exposure region. Therefore, the circuit designs are respectively formed by only a single shot of the lithographic scanner. The uppermost circuit design has a length greater than the length of the maximum exposure region, so that the circuit design is formed by stitching two photomasks lithographically.

Abstract translation: 本发明提供一种包括多个电路设计和设置在电路设计上的最上层电路设计的插入器。 最大曝光区域被定义为可以通过光刻扫描器的单次射击来定义的最大尺寸。 电路设计的最小电路设计尺寸小于最大曝光区域的尺寸。 因此，电路设计分别仅由光刻扫描器的单个镜头形成。 最上面的电路设计的长度大于最大曝光区域的长度，因此电路设计是通过光刻地拼接两个光掩模形成的。

公开(公告)号：US20150014828A1

公开(公告)日：2015-01-15

申请号：US13939184

申请日：2013-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Ming-Tse Lin ,  Kuei-Sheng Wu ,  Chia-Fang Lin

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L23/481 ,  H01L23/535 ,  H01L23/585 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides a semiconductor device with a shielding structure. The semiconductor device includes a substrate, an RF circuit, a shielding structure and an interconnection system. The substrate includes an active side and a back side. The RF circuit is disposed on the active side of the substrate. The shielding structure is disposed on the active side and encompasses the RF circuit. The shielding structure is grounded. The shielding structure includes a shielding TST which does not penetrate through the substrate. The interconnection system is disposed on the active side of the substrate. The interconnection system includes a connecting unit electrically connect a signal to the RF circuit.

Abstract translation: 本发明提供一种具有屏蔽结构的半导体器件。 半导体器件包括衬底，RF电路，屏蔽结构和互连系统。 基板包括有源侧和背面。 RF电路设置在基板的有源侧。 屏蔽结构设置在有源侧并且包围RF电路。 屏蔽结构接地。 屏蔽结构包括不穿透基板的屏蔽TST。 互连系统设置在基板的有源侧。 互连系统包括将信号电连接到RF电路的连接单元。