公开(公告)号：US09748147B1

公开(公告)日：2017-08-29

申请号：US15214467

申请日：2016-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Li-Wei Feng ,  Li-Chieh Hsu ,  Chun-Jen Chen ,  I-Cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L21/20 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/2652 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/8258

Abstract: A method of fabricating an epitaxial layer includes providing a silicon substrate. A dielectric layer covers the silicon substrate. A recess is formed in the silicon substrate and the dielectric layer. A selective epitaxial growth process and a non-selective epitaxial growth process are performed in sequence to respectively form a first epitaxial layer and a second epitaxial layer. The first epitaxial layer does not cover the top surface of the dielectric layer. The recess is filled by the first epitaxial layer and the second epitaxial layer. Finally, the first epitaxial layer and the second epitaxial layer are planarized.

公开(公告)号：US20250015158A1

公开(公告)日：2025-01-09

申请号：US18888191

申请日：2024-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US12040234B2

公开(公告)日：2024-07-16

申请号：US17393387

申请日：2021-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Yu-Fu Wang ,  Min-Hua Tsai ,  Ti-Bin Chen ,  Chih-Chiang Wu ,  Tzu-Chin Wu

IPC: H01L29/49 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/4232 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

公开(公告)号：US20210257471A1

公开(公告)日：2021-08-19

申请号：US17246726

申请日：2021-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66 ,  H01L29/161 ,  H01L29/78

Abstract: A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

公开(公告)号：US20200321442A1

公开(公告)日：2020-10-08

申请号：US16907287

申请日：2020-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.

公开(公告)号：US20200006517A1

公开(公告)日：2020-01-02

申请号：US16053665

申请日：2018-08-02

Applicant: United Microelectronics Corp.

Inventor： Yi-Fan Li ,  Po-Ching Su ,  Cheng-Chia Liu ,  Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Chih-Chiang Wu ,  Ti-Bin Chen ,  Ching-Chu Tseng

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/31

Abstract: A structure of semiconductor device includes a gate structure, disposed on a substrate. A spacer is disposed on a sidewall of the gate structure, wherein the spacer is an l-like structure. A first doped region is disposed in the substrate at two sides of the gate structure. A second doped region is disposed in the substrate at the two sides of the gate structure, overlapping the first doped region. A silicide layer is disposed on the substrate within the second doped region, separating from the spacer by a distance. A dielectric layer covers over the second doped region and the gate structure with the spacer.

公开(公告)号：US10446447B2

公开(公告)日：2019-10-15

申请号：US16036831

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  I-Cheng Hu ,  Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin ,  Chun-Yuan Wu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/311

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.

公开(公告)号：US20190198628A1

公开(公告)日：2019-06-27

申请号：US15853867

申请日：2017-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Kuo-Chin Hung ,  Wen-Yi Teng ,  Ti-Bin Chen

IPC: H01L29/417 ,  H01L29/49 ,  H01L29/423 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes first and second metal gates on a substrate with a gap therebetween. The first metal gate has a first sidewall, and the second metal gate has a second sidewall directly facing the first sidewall. A contact etch stop layer (CESL) is disposed within the gap and extends along the first and second sidewalls. The CESL has a first top portion adjacent to a top surface of the first metal gate and a second top portion adjacent to a top surface of the second metal gate. The first top portion and the second top portion have a trapezoid cross-sectional profile. A first sidewall spacer is disposed on the first sidewall and between the CESL and the first metal gate. A second sidewall spacer is disposed on the second sidewall and between the CESL and the second metal gate.

公开(公告)号：US20180323302A1

公开(公告)日：2018-11-08

申请号：US16036831

申请日：2018-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  I-Cheng Hu ,  Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/823487 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1029 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.

公开(公告)号：US10056490B1

公开(公告)日：2018-08-21

申请号：US15496000

申请日：2017-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  I-Cheng Hu ,  Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/10 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/823487 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1029 ,  H01L29/7851 ,  H01L29/7853

Abstract: A semiconductor device includes: a fin-shaped structure on a substrate, in which a sidewall of the fin-shaped structure comprises a curve. Specifically, the fin-shaped structure includes a top portion and a bottom portion, a shallow trench isolation (STI) around the bottom portion of the fin-shaped structure, and the curve includes a planar portion extending from the top surface of fin-shaped structure downward and a curved portion extending from the bottom surface of the fin-shaped structure upward.