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    Layout of semiconductor memory device
    11.
    发明授权
    Layout of semiconductor memory device 有权

    公开(公告)号：US11915755B2

    公开(公告)日：2024-02-27

    申请号：US17580591

    申请日：2022-01-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

    IPC: G11C15/04

    CPC classification number: G11C15/04

    Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

    Method of forming static random-access memory (SRAM) cell array
    16.
    发明授权
    Method of forming static random-access memory (SRAM) cell array 有权

    公开(公告)号：US10468420B2

    公开(公告)日：2019-11-05

    申请号：US16028442

    申请日：2018-07-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

    IPC: H01L21/336 ,  H01L27/11 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84

    Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

    Control circuit used for ternary content-addressable memory with two logic units
    18.
    发明授权
    Control circuit used for ternary content-addressable memory with two logic units 有权

    公开(公告)号：US10366756B1

    公开(公告)日：2019-07-30

    申请号：US16104946

    申请日：2018-08-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Shu-Ru Wang

    IPC: G11C15/00 ,  G11C15/04

    Abstract: A control circuit for a ternary content-addressable memory includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line and a second power supply line. When voltages at the first search line and the second search line match voltages at the first storage unit and the second storage unit, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.

    Semiconductor memory device
    19.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10134449B2

    公开(公告)日：2018-11-20

    申请号：US15589985

    申请日：2017-05-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chien-Hung Chen ,  Meng-Ping Chuang ,  Tong-Yu Chen ,  Yu-Tse Kuo

    IPC: G11C5/02 ,  G11C11/412 ,  H01L27/11

    Abstract: A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

    Static random-access memory (SRAM) cell array and forming method thereof
    20.
    发明授权
    Static random-access memory (SRAM) cell array and forming method thereof 有权

    公开(公告)号：US10050046B2

    公开(公告)日：2018-08-14

    申请号：US15691764

    申请日：2017-08-31

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

    IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66

    Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

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