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    ASYMMETRIC PROCESSOR WITH CORES THAT SUPPORT DIFFERENT ISA INSTRUCTION SUBSETS
    11.
    发明申请
    ASYMMETRIC PROCESSOR WITH CORES THAT SUPPORT DIFFERENT ISA INSTRUCTION SUBSETS 审中-公开
    不相称的处理器，支持不同的ISA指令服务

    公开(公告)号：US20160162293A1

    公开(公告)日：2016-06-09

    申请号：US14956541

    申请日：2015-12-02

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： RODNEY E. HOOKER ,  TERRY PARKS ,  G. GLENN HENRY

    IPC: G06F9/30

    CPC classification number: G06F9/3009 ,  G06F1/3206 ,  G06F1/3293 ,  G06F9/5044 ,  Y02D10/122

    Abstract: An asymmetric multi-core processor uses at least two asymmetric cores to collectively support the instructions of an instruction set architecture (ISA). A general-feature core and a special feature core that support different instruction subsets of the ISA. A switch manager detects whether a thread includes an instruction that is not supported by the currently-executing core and, after detecting such an instruction, switches the thread to the other core.

    Abstract translation: 非对称多核处理器使用至少两个不对称核来共同支持指令集架构（ISA）的指令。 通用功能核心和支持ISA不同指令子集的特殊功能核心。 交换机管理器检测线程是否包括当前执行的核心不支持的指令，并且在检测到这样的指令之后，将线程切换到另一个核心。

    PROCESSOR THAT RECOVERS FROM EXCESSIVE APPROXIMATE COMPUTING ERROR
    13.
    发明申请
    PROCESSOR THAT RECOVERS FROM EXCESSIVE APPROXIMATE COMPUTING ERROR 有权
    处理器从过大的近似计算错误中恢复

    公开(公告)号：US20150227429A1

    公开(公告)日：2015-08-13

    申请号：US14522520

    申请日：2014-10-23

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

    IPC: G06F11/14

    CPC classification number: G06F11/1446 ,  G06F9/30014 ,  G06F9/30185 ,  G06F9/38 ,  G06F9/3863 ,  G06F11/0754 ,  G06F11/0793 ,  G06F11/1402 ,  G06F11/1435 ,  G06F2201/84

    Abstract: A processor includes a storage configured to receive a snapshot of a state of the processor prior to performing a set of computations in an approximating manner. The processor also includes an indicator that indicates an amount of error accumulated while the set of computations is performed in the approximating manner. When the processor detects that the amount of error accumulated has exceeded an error bound, the processor is configured to restore the state of the processor to the snapshot from the storage.

    Abstract translation: 处理器包括被配置为在以近似方式执行一组计算之前接收处理器状态的快照的存储器。 处理器还包括指示器，其指示在以近似方式执行计算集合时累积的误差量。 当处理器检测到累积的错误量超过了错误限制时，处理器被配置为将处理器的状态从存储恢复到快照。

    FUSE-ENABLED SECURE BIOS MECHANISM WITH OVERRIDE FEATURE
    14.
    发明申请
    FUSE-ENABLED SECURE BIOS MECHANISM WITH OVERRIDE FEATURE 有权

    公开(公告)号：US20170046517A1

    公开(公告)日：2017-02-16

    申请号：US15338620

    申请日：2016-10-31

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. GLENN HENRY

    IPC: G06F21/57 ,  G06F21/78 ,  H04L9/06

    CPC classification number: G06F21/572 ,  G06F21/78 ,  G06F2221/2139 ,  H04L9/0631 ,  H04L9/0643

    Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, a JTAG control chain, a fuse, a machine specific register, and an access controller. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest, where the encrypted message digest has an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is operatively coupled to the BIOS ROM, and is configured to generate a BIOS check interrupt at a combination of prescribed intervals and event occurrences, and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest, and is configured to compare the second message digest with the decrypted message digest, and is configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The random number generator disposed within the microprocessor, and generates a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied. The JTAG control chain is configured to program the combination of prescribed intervals and event occurrences within tamper detection microcode storage. The fuse is configured to indicate whether programming of the combination of prescribed intervals and event occurrences is to be disabled. The machine specific register is configured to store a value therein. The access control element is coupled to the fuse, the machine specific register, and the JTAG control chain, and is configured to determine that the fuse is blown, and configured to direct the JTAG control chain to enable programming of the combination of prescribed intervals and event occurrences if the value matches an override value within the access control element during a period that the value is stored within the machine specific register.

    POWER MANAGEMENT SYNCHRONIZATION MESSAGING SYSTEM
    16.
    发明申请
    POWER MANAGEMENT SYNCHRONIZATION MESSAGING SYSTEM 有权
    电源管理同步消息传递系统

    公开(公告)号：US20160209897A1

    公开(公告)日：2016-07-21

    申请号：US14980209

    申请日：2015-12-28

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. GLENN HENRY ,  DARIUS D. GASKINS

    IPC: G06F1/26

    CPC classification number: G06F1/26 ,  G06F1/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30083 ,  G06F9/44505 ,  G06F9/5094 ,  G06F11/1423 ,  G06F11/3664 ,  G06F13/36 ,  G06F15/163 ,  G06F15/82 ,  Y02D10/14 ,  Y02D10/22

    Abstract: A multi-die package for a microprocessor provides a power management synchronization system. The package has a plurality of dies. Each die has a plurality of cores, including a single master core. A plurality of sideband non-system-bus inter-die communication wires communicatively couple the dies to each other for a purpose of synchronizing power management. The master core of each die is configured to use one and only one of the inter-die communication wires to transmit power management synchronization messages to each of the other master cores. The master core of each die is also configured to receive power management synchronization messages from each of the other master cores via one or more inter-die communication wires. The cores use this system of inter-die communication wires to synchronize management of resources that affect both the performance and power consumption of the cores.

    Abstract translation: 用于微处理器的多管芯封装提供电源管理同步系统。 该封装具有多个管芯。 每个管芯具有多个芯，包括单个母芯。 为了同步电源管理的目的，多个边带非系统总线芯片间通信线通信地将管芯彼此连接。 每个管芯的主核心被配置为使用芯片间通信线中的一个且仅一个将功率管理同步消息发送到每个其他主核。 每个裸片的主核心还被配置为经由一个或多个芯片间通信线路从每个其他主核心接收功率管理同步消息。 内核使用这种芯片间通信线系统来同步影响内核性能和功耗的资源管理。

    MICROPROCESSOR WITH ARM AND X86 INSTRUCTION LENGTH DECODERS
    17.
    发明申请
    MICROPROCESSOR WITH ARM AND X86 INSTRUCTION LENGTH DECODERS 有权
    具有ARM和X86指令长度解码器的微处理器

    公开(公告)号：US20160202980A1

    公开(公告)日：2016-07-14

    申请号：US14963134

    申请日：2015-12-08

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

    IPC: G06F9/30 ,  G06F12/08

    CPC classification number: G06F9/3016 ,  G06F9/30025 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/4401 ,  G06F12/0875 ,  G06F2212/452

    Abstract: A microprocessor natively translates and executes instructions of both the x86 instruction set architecture (ISA) and the Advanced RISC Machines (ARM) ISA. An instruction formatter extracts distinct ARM instruction bytes from a stream of instruction bytes received from an instruction cache and formats them. ARM and x86 instruction length decoders decode ARM and x86 instruction bytes, respectively, and determine instruction lengths of ARM and x86 instructions. An instruction translator translates the formatted x86 ISA and ARM ISA instructions into microinstructions of a unified microinstruction set architecture of the microprocessor. An execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.

    Abstract translation: 微处理器本地翻译和执行x86指令集架构（ISA）和高级RISC机器（ARM）ISA的指令。 指令格式化器从指令高速缓存接收的指令字节流中提取不同的ARM指令字节，并对其进行格式化。 ARM和x86指令长度解码器分别解码ARM和x86指令字节，并确定ARM和x86指令的指令长度。 指令翻译器将格式化的x86 ISA和ARM ISA指令转换为微处理器的统一微指令集架构的微指令。 执行流水线执行微指令以生成由x86 ISA和ARM ISA指令定义的结果。

    MULTI-CORE MICROPROCESSOR POWER GATING CACHE RESTORAL MECHANISM
    19.
    发明申请
    MULTI-CORE MICROPROCESSOR POWER GATING CACHE RESTORAL MECHANISM 有权
    多核心微处理器功率增益缓存机制

    公开(公告)号：US20150339231A1

    公开(公告)日：2015-11-26

    申请号：US14285484

    申请日：2014-05-22

    Applicant: VIA TECHNOLOGIES, INC.

    Inventor： G. GLENN HENRY ,  DINESH K. JAIN ,  STEPHAN GASKINS

    IPC: G06F12/08 ,  G06F9/44

    CPC classification number: G06F12/0844 ,  G06F9/4418 ,  G06F2212/601 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

    Abstract: An apparatus includes a fuse array and a stores. The fuse array is disposed on a die, and is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompresses the compressed configuration data, and stores a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the caches.

    Abstract translation: 一种装置包括熔丝阵列和商店。 保险丝阵列设置在管芯上，并且用多个芯的压缩配置数据进行编程。 存储器耦合到多个核心，并且包括多个子存储器，每个子存储器对应于多个核心中的每一个，多个核心中的一个核心在上电/复位时访问半导体熔丝阵列以读取，以及 对压缩的配置数据进行解压缩，并将多个解压缩的配置数据集合存储在多个子存储器中的多个核心的每个内的一个或多个高速缓存存储器中，并且其中，在电源门控事件之后， 随后访问多个子存储中的每个子存储器中的相应的一个，以检索和使用解压缩的配置数据集来初始化高速缓存。

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