公开(公告)号：US20150339231A1

公开(公告)日：2015-11-26

申请号：US14285484

申请日：2014-05-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  DINESH K. JAIN ,  STEPHAN GASKINS

IPC: G06F12/08 ,  G06F9/44

CPC classification number: G06F12/0844 ,  G06F9/4418 ,  G06F2212/601 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a stores. The fuse array is disposed on a die, and is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompresses the compressed configuration data, and stores a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the caches.

Abstract translation: 一种装置包括熔丝阵列和商店。 保险丝阵列设置在管芯上，并且用多个芯的压缩配置数据进行编程。 存储器耦合到多个核心，并且包括多个子存储器，每个子存储器对应于多个核心中的每一个，多个核心中的一个核心在上电/复位时访问半导体熔丝阵列以读取，以及 对压缩的配置数据进行解压缩，并将多个解压缩的配置数据集合存储在多个子存储器中的多个核心的每个内的一个或多个高速缓存存储器中，并且其中，在电源门控事件之后， 随后访问多个子存储中的每个子存储器中的相应的一个，以检索和使用解压缩的配置数据集来初始化高速缓存。

公开(公告)号：US20170068546A1

公开(公告)日：2017-03-09

申请号：US15357145

申请日：2016-11-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  STEPHAN GASKINS

IPC: G06F9/38 ,  G06F13/42 ,  G06F9/44 ,  G06F13/24

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to generate a default core ID and to sample the indicator. When the indicator indicates a first predetermined value, the default core ID generated by a default one of the plurality of processing cores designates the default processing core to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to generate alternate core IDs that are different from the default core IDs. One of the alternate core IDs designates an alternate processing core, other than the default processing core, to be the bootstrap processor.

Abstract translation: 微处理器包括指示器和多个处理核心。 多个处理核心中的每一个被配置为生成默认核心ID并对指示器进行采样。 当指示符指示第一预定值时，由多个处理核心中的默认核心ID产生的默认核心ID将默认处理核心指定为引导处理器。 当指示符指示与第一预定值不同的第二预定值时，多个处理核被配置为生成与默认核心ID不同的替代核心ID。 替代核心ID之一指定除了默认处理核心之外的替代处理核心，作为自举处理器。

公开(公告)号：US20170003707A1

公开(公告)日：2017-01-05

申请号：US15265127

申请日：2016-09-14

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  BRENT BEAN ,  STEPHAN GASKINS

IPC: G06F1/12 ,  G06F1/32 ,  G06F9/44

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract translation: 微处理器包括多个核心，共享高速缓冲存储器和控制单元，其通过停止其时钟信号来单独地将每个核心置于睡眠状态。 每个核心执行睡眠指令，并且响应地使控制单元的相应请求将核心置于睡眠状态，控制单元响应地进行该操作，并且检测所有核心何时完成了各自的请求，并且响应地只唤醒最后请求的核心 。 最后一个内核写回并使共享高速缓存内存无效，并指示它已被无效，并向控制单元发出请求以使最后一个核心返回休眠状态。 控制单元将最后一个核心置于休眠状态，并持续保持其他内核处于睡眠状态，同时最后一个内核回写并使共享缓存内存无效，表示共享高速缓存内存无效，并返回睡眠状态。

公开(公告)号：US20150339232A1

公开(公告)日：2015-11-26

申请号：US14285517

申请日：2014-05-22

Applicant: VIA Technologies, Inc.

Inventor： G. GLENN HENRY ,  DINESH K. JAIN ,  STEPHAN GASKINS

IPC: G06F12/08 ,  G06F9/44

CPC classification number: G06F12/0844 ,  G06F9/4403 ,  G06F9/4418 ,  G06F12/0638 ,  G06F12/0875 ,  G06F15/177 ,  G06F2212/401 ,  G06F2212/601 ,  G11C7/20 ,  G11C17/16

Abstract: An apparatus includes a fuse array, a stores, and a plurality of cores. The fuse array is programmed with compressed configuration data. The stores is for storage and access of decompressed configuration data sets. One of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store the decompressed configuration data sets for one or more cache memories in the stores. Each of the plurality of cores includes reset logic and sleep logic. The reset logic is configured to employ the decompressed configuration data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic is configured to determine that power is restored following a power gating event, and is configured to subsequently access the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event.

Abstract translation: 一种装置包括熔丝阵列，存储器和多个核。 保险丝阵列用压缩配置数据编程。 存储用于存储和访问解压缩的配置数据集。 多个核心中的一个核心在加电/复位时访问熔丝阵列以读取和解压缩压缩的配置数据，并将存储器中的一个或多个高速缓冲存储器的解压缩配置数据集存储起来。 多个核心中的每一个包括复位逻辑和睡眠逻辑。 复位逻辑被配置为在上电/复位时使用解压缩的配置数据集来初始化一个或多个高速缓存存储器。 休眠逻辑被配置为确定在电源门控事件之后恢复电力，并且被配置为随后访问存储以检索和使用解压缩的配置数据集来初始化电源门控事件之后的一个或多个高速缓存。

公开(公告)号：US20150338904A1

公开(公告)日：2015-11-26

申请号：US14285412

申请日：2014-05-22

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  DINESH K. JAIN ,  STEPHAN GASKINS

IPC: G06F1/32 ,  G06F12/08 ,  G06F9/44 ,  G06F12/12

CPC classification number: G06F12/0893 ,  G06F1/3275 ,  G06F8/66 ,  G06F9/4403 ,  G06F12/0811 ,  G06F12/12 ,  G06F15/177 ,  G06F2212/222 ,  G06F2212/283 ,  G06F2212/601 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

Abstract translation: 一种装置包括熔丝阵列和多个芯。 保险丝阵列用压缩数据编程。 多个核心中的每一个在上电/复位时访问熔丝阵列以读取和解压缩压缩数据，并且在耦合的存储器中存储多个核心中的每一个内的一个或多个高速缓冲存储器的解压缩数据集 到多个核心中的每一个。 多个核心中的每一个具有复位逻辑和睡眠逻辑。 复位逻辑采用解压缩数据集在上电/复位时初始化一个或多个高速缓存存储器。 休眠逻辑确定在电源门控事件之后恢复电力，并且随后访问存储以检索和使用解压缩数据集来初始化电源门控事件之后的一个或多个高速缓存。

公开(公告)号：US20150046680A1

公开(公告)日：2015-02-12

申请号：US14522931

申请日：2014-10-24

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  STEPHAN GASKINS

IPC: G06F9/445 ,  G06F15/82

CPC classification number: G06F1/26 ,  G06F1/24 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30076 ,  G06F9/30083 ,  G06F9/44505 ,  G06F9/5094 ,  G06F11/1423 ,  G06F11/3664 ,  G06F13/36 ,  G06F15/163 ,  G06F15/82 ,  Y02D10/14 ,  Y02D10/22

Abstract: A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.

Abstract translation: 一种用于动态重新配置多核微处理器的一个或多个核心的方法，所述多核微处理器包括多个核心和边带通信线路，其外部连接到连接到芯片组的系统总线，这有助于非系统总线核心间通信。 为了构建基于边带的核心间通信的目的，至少一些核可操作以可重新配置地指定或不具有主凭证。 该方法包括确定微处理器的核心的初始配置，该配置指定至少一个核心，但不将所有核心指定为主核心，并且根据修改的配置重新配置核心，该修改的配置删除主命名 从最初如此指定的核心，并将主指定分配给最初未指定的核心。 每个核心被配置为基于其指定或不存在作为主核心有条件地驱动其所连接的边带通信线。

公开(公告)号：US20160349824A1

公开(公告)日：2016-12-01

申请号：US15232506

申请日：2016-08-09

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  STEPHAN GASKINS

IPC: G06F1/32 ,  G06F9/30 ,  G06F12/084 ,  G06F1/12 ,  G06F13/24 ,  G06F12/0875 ,  G06F9/38 ,  G06F1/04

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

公开(公告)号：US20150338905A1

公开(公告)日：2015-11-26

申请号：US14285448

申请日：2014-05-22

Applicant: Via Technologies, Inc.

Inventor： G. GLENN HENRY ,  DINESH K. JAIN ,  STEPHAN GASKINS

IPC: G06F1/32 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F3/0631 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0866 ,  G06F12/12 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/601 ,  G06F2212/608 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C29/787 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

Abstract translation: 一种装置包括熔丝阵列和商店。 保险丝阵列用多个核心的压缩配置数据编程。 存储器耦合到多个核心，并且包括多个子存储器，每个子存储器对应于多个核心中的每一个，多个核心中的一个核心在上电/复位时访问半导体熔丝阵列以读取，以及 对压缩的配置数据进行解压缩，并且在多个子存储器中的多个核心的每个内存储一个或多个高速缓存存储器的多个解压配置数据集。 多个核心中的每一个具有睡眠逻辑。 睡眠逻辑被配置为随后访问多个子商店中的每一个的对应的一个，以检索并使用解压配置数据集来初始化电源门控事件之后的一个或多个高速缓存。