公开(公告)号：US10185571B2

公开(公告)日：2019-01-22

申请号：US15618010

申请日：2017-06-08

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Timothy P. Mann ,  Alexander Fainkichen

IPC: G06F12/00 ,  G06F13/00 ,  G06F9/4401 ,  G06F12/109 ,  G06F11/22 ,  G06F11/27 ,  G06F9/455

Abstract: A method of re-mapping memory regions for firmware run-time services to a virtual address space of a kernel executed on a processor, includes the steps of selecting a re-mapping policy for re-mapping the memory regions for the firmware run-time services, creating a new mapping according to the selected re-mapping policy, and making a call to an application programming interface exposed by the firmware to apply the new map and re-map the memory regions for the firmware to the virtual address space of the kernel.

公开(公告)号：US20180173539A1

公开(公告)日：2018-06-21

申请号：US15387332

申请日：2016-12-21

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyrien Laplace ,  Alexander Fainkichen ,  Ye Li ,  Regis Duchesne

IPC: G06F9/44 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F9/4401 ,  G06F12/109 ,  G06F12/1441 ,  G06F2212/1008 ,  G06F2212/657

Abstract: Examples construct a bootloader address space using a page fault exception. A bootloader executing in machine address (MA) space determines the MA at which the bootloader has been loaded into memory. The bootloader calculates a difference between an expected virtual address (VA) and the loaded MA. The bootloader defines a page table mapping the bootloader MA to an expected VA, and sets an exception handling vector to point to the expected VA. When a memory management unit (MMU) utilizing the defined page table for address translation is enabled, a page fault exception occurs. The page fault exception handling resumes execution of the bootloader at the expected VA via an exception handling vector pointing thereto.

公开(公告)号：US09952895B2

公开(公告)日：2018-04-24

申请号：US14876831

申请日：2015-10-07

Applicant: VMWARE, INC.

Inventor： Andrei Warkentin ,  Irfan Ulla Khan ,  Cyprien Laplace ,  Harvey Tuch ,  Alexander Fainkichen

IPC: G06F13/24 ,  G06F13/00 ,  G06F9/48 ,  G06F13/26

CPC classification number: G06F9/4818 ,  G06F13/26

Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes the steps of obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a regular interrupt, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector, and disabling interrupts in the processor. On the other hand, if the received interrupt is a PNMI, a PNMI interrupt handler is executed using the interrupt vector as an input thereto.

公开(公告)号：US09769120B2

公开(公告)日：2017-09-19

申请号：US14994383

申请日：2016-01-13

Applicant: VMware, Inc.

Inventor： Alexander Fainkichen ,  Craig Newell

IPC: G06F21/00 ,  H04L29/06 ,  C09J7/04 ,  B32B37/16 ,  H04W12/06 ,  H04W12/08 ,  H04W4/00 ,  G06F9/445 ,  G06F9/455 ,  G06F3/0482 ,  G06F3/0484 ,  H04M1/725 ,  H04W76/02 ,  H04L12/24 ,  H04W68/12

CPC classification number: H04L63/108 ,  B32B5/024 ,  B32B27/12 ,  B32B27/38 ,  B32B37/025 ,  B32B37/12 ,  B32B37/16 ,  B32B2037/1253 ,  C08J5/128 ,  C08J5/24 ,  C08J2363/04 ,  C08J2367/00 ,  C09J7/21 ,  C09J7/30 ,  C09J163/04 ,  C09J2463/00 ,  C09J2467/006 ,  G06F3/0482 ,  G06F3/04842 ,  G06F9/445 ,  G06F9/455 ,  G06F9/45529 ,  G06F9/45558 ,  G06F21/6245 ,  G06F21/629 ,  G06F2009/45587 ,  G06F2009/45595 ,  H04L41/0853 ,  H04L63/0272 ,  H04L63/102 ,  H04L63/105 ,  H04L63/20 ,  H04L67/34 ,  H04M1/72522 ,  H04M1/72583 ,  H04W4/50 ,  H04W4/60 ,  H04W8/22 ,  H04W12/06 ,  H04W12/08 ,  H04W68/12 ,  H04W76/10 ,  Y10T428/14

Abstract: One embodiment of the present invention provides a system for providing exclusive access to a virtual private network (VPN) connection to an authorized application. During operation, the system creates a unique network namespace that is different from a default network namespace of a host system. The system then places a pseudo network interface associated with the VPN connection into the unique network namespace. Furthermore, the system places at least one socket for an authorized application into the unique network namespace. The system also precludes unauthorized applications on the host from accessing the unique network namespace, thereby facilitating exclusive access to the VPN connection by the authorized application.

公开(公告)号：US20230325222A1

公开(公告)日：2023-10-12

申请号：US17715292

申请日：2022-04-07

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Sunil Kotian ,  Ye Li ,  Cyprien Laplace ,  Regis Duchesne ,  Alexander Fainkichen ,  Shruthi Hiriyuru

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45595

Abstract: Disclosed are various examples of lifecycle and recovery management for virtualized data processing unit (DPU) management operating systems. A DPU device executes a DPU management hypervisor that communicates with a management service over a network. The DPU management hypervisor virtualizes DPU hardware resources and passes control of the virtualized DPU hardware resources to a DPU management operating system (OS) virtual machine (VM). The DPU management hypervisor maintains control of a management network interface card (NIC) of the DPU device.

公开(公告)号：US20230237010A1

公开(公告)日：2023-07-27

申请号：US17580866

申请日：2022-01-21

Applicant: VMware, Inc.

Inventor： Regis Duchesne ,  Andrei Warkentin ,  Cyprien Laplace ,  Ye Li ,  Alexander Fainkichen ,  Shruthi Hiriyuru ,  Sunil Kotian

IPC: G06F15/78 ,  G06F9/30

CPC classification number: G06F15/7842 ,  G06F9/30123

Abstract: Disclosed are various examples of providing provide efficient waiting for detection of memory value updates for Advanced RISC Machines (ARM) architectures. An ARM processor component instructs a memory agent to perform a processing action, and executes a waiting function. The waiting function ensures that the processing action is completed by the memory agent. The waiting function performs an exclusive load at a memory location, and a wait for event (WFE) instruction that causes the ARM processor component to wait in a low-power mode for an event register to be set. Once the event register is set, the waiting function completes and a second processing action is executed by the ARM processor component.

公开(公告)号：US20230122654A1

公开(公告)日：2023-04-20

申请号：US18069851

申请日：2022-12-21

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Alexander Fainkichen ,  Ye Li ,  Regis Duchesne ,  Cyprien Laplace ,  Shruthi Hiriyuru ,  Sunil Kotian

IPC: G06F12/06 ,  G06F9/455 ,  G06F13/16 ,  G06F13/42

Abstract: Techniques for enabling efficient guest OS access to PCIe configuration space are provided. In one set of embodiments, a hypervisor can reserve a single host physical memory page in the host physical memory of a host system and can populate the single host physical memory page with a value indicating non-presence of PCIe device functions. The hypervisor can then create, for each guest physical memory page in a guest physical memory of a virtual machine (VM) corresponding to a PCIe configuration space of an absent PCIe device function in the VM, a mapping in the hypervisor's second-level page tables that maps the guest physical memory page to the single host physical memory page.

公开(公告)号：US11579918B2

公开(公告)日：2023-02-14

申请号：US17476090

申请日：2021-09-15

Applicant: VMware, Inc.

Inventor： Andrei Warkentin ,  Cyprien Laplace ,  Regis Duchesne ,  Ye Li ,  Alexander Fainkichen

IPC: G06F9/455 ,  G06F11/34 ,  G06F1/3287 ,  G06F1/3234 ,  G06F9/50 ,  G06F11/30 ,  G06F1/329 ,  G06F9/48

Abstract: Techniques for optimizing CPU usage in a host system based on VM guest OS power and performance management are provided. In one embodiment, a hypervisor of the host system can capture information from a VM guest OS that pertains to a target power or performance state set by the guest OS for a vCPU of the VM. The hypervisor can then perform, based on the captured information, one or more actions that align usage of host CPU resources by the vCPU with the target power or performance state.

公开(公告)号：US11513825B2

公开(公告)日：2022-11-29

申请号：US16671086

申请日：2019-10-31

Applicant: VMware, Inc.

Inventor： Ye Li ,  David Ott ,  Cyprien Laplace ,  Andrei Warkentin ,  Alexander Fainkichen

IPC: G06F9/54 ,  G06F9/455 ,  G06F9/30 ,  G06F13/42

Abstract: System and method for providing trusted execution environments uses a peripheral component interconnect (PCI) device of a computer system to receive and process commands to create and manage a trusted execution environment for a software process running in the computer system. The trusted execution environment created in the PCI device is then used to execute operations for the software process.

公开(公告)号：US11210222B2

公开(公告)日：2021-12-28

申请号：US15878062

申请日：2018-01-23

Applicant: VMware, Inc.

Inventor： Ye Li ,  Cyprien Laplace ,  Andrei Warkentin ,  Alexander Fainkichen ,  Regis Duchesne

IPC: G06F12/0815 ,  G06F12/0808

Abstract: An example method of maintaining cache coherency in a virtualized computing system includes: trapping access to a memory page by guest software in a virtual machine at a hypervisor managing the virtual machine, where the memory page is not mapped in a second stage page table managed by the hypervisor; performing cache coherency maintenance for instruction and data caches of a central processing unit (CPU) in the virtualized computing system in response to the trap; mapping the memory page in the second stage page table with execute permission; and resuming execution of the virtual machine.