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公开(公告)号：US5828868A
公开(公告)日：1998-10-27
申请号：US746606
申请日：1996-11-13
CPC分类号： G06F9/3842 , G06F1/08 , G06F15/7832 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3863 , G06F9/3869
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
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公开(公告)号：US4825108A
公开(公告)日：1989-04-25
申请号：US63569
申请日：1987-06-15
IPC分类号： H03K19/013 , H03K19/018 , H03K19/092 , H03K17/04 , H03K17/60 , H03K19/088
CPC分类号： H03K19/013 , H03K19/01806
摘要： A voltage translator containing a bipolar transistor (Q1), a rectifier (10), a resistor (R1), and a first clamp (12) converts an input voltage (V.sub.I) into one or more output voltages of restricted voltage swing. The first clamp clamps the emitter voltage of the transistor when it is turned on. In one version, the translator includes a second clamp (14) that clamps the collector voltage of the translator when it is turned off. The translator then provides an output voltage (V.sub.O) inverse to the input voltage. In another version, the first clamp is connected between a voltage supply (V.sub.EE) and the emitter of the transistor. Its collector is connected directly to another voltage supply (V.sub.CC) so that the translator only makes non-inverting translations.
摘要翻译： 包含双极晶体管（Q1），整流器（10），电阻器（R1）和第一钳位电压（12）的电压转换器将输入电压（VI）转换成受限制的电压摆幅的一个或多个输出电压。 当晶体管导通时，第一个钳位钳位晶体管的发射极电压。 在一个版本中，翻译器包括第二夹具（14），其在翻转器关闭时夹紧翻译器的集电极电压。 翻译器然后提供与输入电压相反的输出电压（＆amp; upbar＆VO）。 在另一个版本中，第一钳位电路连接在电压源（VEE）和晶体管的发射极之间。 其收集器直接连接到另一个电压源（VCC），以便转换器仅进行非反相转换。
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公开(公告)号：US4740717A
公开(公告)日：1988-04-26
申请号：US934753
申请日：1986-11-25
申请人： Thomas D. Fletcher , Yong-In Shin
发明人： Thomas D. Fletcher , Yong-In Shin
IPC分类号： H03K3/353 , H03K3/3565 , H03K17/30 , H03K17/687 , H03K19/003 , H03K17/16 , H03K19/094
CPC分类号： H03K3/3565 , H03K19/00361
摘要： A switching device (22) responsive to an input voltage V.sub.A is powered by low and high internal supply voltages V.sub.L and V.sub.H. The device changes state as V.sub.A -V.sub.L passes a threshold voltage V.sub.T. After the device makes a desired change of state in response to rising V.sub.A, a hysteresis circuit (24) temporarily decreases V.sub.T below that which would otherwise be present. Likewise, after the device makes a desired change of state in the opposite direction when V.sub.A is falling, the hysteresis circuit temporarily decreases V.sub.T. In both cases, V.sub.T later automatically returns to its original value. This dynamic hysteresis prevents spikes in V.sub.L and V.sub.H from causing undesired changes in state.
摘要翻译： 响应于输入电压VA的开关装置（22）由低和高内部电源电压VL和VH供电。 当VA-VL通过阈值电压VT时，器件改变状态。 在器件响应于升高的VA之后进行期望的状态改变时，滞后电路（24）暂时将VT降低到低于否则将存在的VT。 同样地，当VA在下降时，在相反方向进行期望的状态改变之后，滞后电路暂时降低VT。 在这两种情况下，VT稍后自动返回到其原始值。 该动态滞后可防止VL和VH中的尖峰引起不期望的状态变化。
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14.发明授权Bipolar logic gate including circuitry to prevent turn-off and deep saturation of pull-down transistor 失效双极逻辑门包括用于防止下拉晶体管的截止和深度饱和的电路
公开(公告)号：US4415817A
公开(公告)日：1983-11-15
申请号：US309756
申请日：1981-10-08
申请人： Thomas D. Fletcher
发明人： Thomas D. Fletcher
IPC分类号： H03K19/018 , H03K19/013 , H03K17/04 , H03K17/62 , H03K19/084 , H03K19/088
CPC分类号： H03K19/013
摘要： A logic circuit in which (1) a first bipolar transistor has a base, an emitter, and a collector coupled to a voltage/current source, and (2) a second bipolar transistor has a base coupled to the emitter of the first transistor, an emitter coupled to a constant voltage source, and a collector coupled to the voltage/current source contains operational control circuitry for preventing the second transistor from either turning off or normally going into deep saturation. Each transistor is typically an NPN device. The operational control circuitry may then comprise (1) first circuitry for providing current from the voltage/current source in a single current-flow direction to the collector of the second transistor and (2) second circuitry for providing current from the first circuitry in a single current-flow direction to the base of the second transistor. Optimally, the first circuitry prevents the second transistor from ever going into deep saturation.
摘要翻译： 一种逻辑电路，其中（1）第一双极晶体管具有耦合到电压/电流源的基极，发射极和集电极，以及（2）第二双极晶体管具有耦合到第一晶体管的发射极的基极， 耦合到恒定电压源的发射极和耦合到电压/电流源的集电极包含用于防止第二晶体管截止或正常进入深度饱和的操作控制电路。 每个晶体管通常是NPN器件。 然后，操作控制电路可以包括（1）用于将电流/电流源的电流以单电流流动方向提供给第二晶体管的集电极的第一电路，以及（2）用于在第一电路中提供来自第一电路的电流的第二电路 单电流流向第二晶体管的基极。 最佳地，第一电路防止第二晶体管进入深度饱和。
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公开(公告)号：US20140052969A1
公开(公告)日：2014-02-20
申请号：US13976997
申请日：2011-12-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3893
摘要： A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.
摘要翻译： 描述处理核心，其具有执行单元逻辑电路，其具有第一寄存器以存储第一向量输入操作数，第二寄存器存储第二向量输入操作数和第三寄存器以存储包含标量输入操作数a，b的打包数据结构 ， C。 执行单元逻辑电路还包括执行操作的乘法器（a *（第一向量输入操作数））+（b *（第二向量操作数））+ c。
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公开(公告)号：US07325025B2
公开(公告)日：2008-01-29
申请号：US10020447
申请日：2001-12-18
申请人： Thomas D. Fletcher
发明人： Thomas D. Fletcher
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： A look-ahead carry adder circuit has multiple stages that are grouped into a carry generation blocks. The size of one of the carry generation blocks is three stages. There may be other carry generation blocks that are of a size that is a whole number multiple of three stages. In an embodiment, the look-ahead carry adder has only one critical path. In a further embodiment, the load on the critical path is minimized by using buffers.
摘要翻译： 先行进位加法器电路具有被分组为进位发生块的多个级。 进位发生块之一的大小是三个阶段。 可以存在其他携带生成块的大小是三个阶段的整数倍。 在一个实施例中，先行进位加法器仅具有一个关键路径。 在另一个实施例中，通过使用缓冲器使关键路径上的负载最小化。
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17.发明授权Method and apparatus for correcting a clock duty cycle in a clock distribution network 有权用于校正时钟分配网络中的时钟占空比的方法和装置公开(公告)号：US06750689B2
公开(公告)日：2004-06-15
申请号：US09823098
申请日：2001-03-29
IPC分类号： H03K3017
CPC分类号： H03K5/1565 , H03K5/15013
摘要： A clock duty cycle correction circuit. The duty cycle correction circuit is located at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.
摘要翻译： 时钟占空比校正电路。 占空比校正电路位于时钟分配网络中的接收器处，以校正分布式时钟信号的占空比。
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公开(公告)号：US06667645B1
公开(公告)日：2003-12-23
申请号：US09467214
申请日：1999-12-20
申请人： Thomas D. Fletcher , Eitan Rosen
发明人： Thomas D. Fletcher , Eitan Rosen
IPC分类号： H03K3356
CPC分类号： H03K5/15013 , G06F1/10 , H03K19/0963
摘要： A signal transfer clocking circuit is disclosed which features a first stage including a first latch and a first, non-clocking circuit in series therewith and a second stage including a second, dynamic latch and at least a second circuit in series therewith. The first latch has a data input side and is opened in response to a first level of a pulse clock signal applied thereto to effect transfer of incoming data through the first stage in a first phase of operation of the signal transfer clocking circuit. The dynamic latch has a data input coupled to an output of the first circuit and is opened in response to a second level of the same or different pulse clock signal applied thereto as that applied to the first latch to effect transfer of data generated by the first stage, through the second stage, to at least one succeeding circuit, in a second, successive phase of operation of the signal transfer clocking circuit, the succeeding circuit being opened and closed by a clock signal having phase and frequency characteristics linked to that applied to the dynamic latch. The dynamic latch clocking methodology used in the signal transfer clocking circuit is particularly applicable to any traditional static latch circuits, such as CMOS static latch circuitry, although not limited thereto, to minimize min-delay race violations and to effect a skew-tolerant operation.
摘要翻译： 公开了一种信号传输时钟电路，其特征在于包括第一锁存器和与其串联的第一非时钟电路的第一级和包括第二动态锁存器和至少第二电路串联的第二级。 第一锁存器具有数据输入端，并且响应于施加到其上的脉冲时钟信号的第一电平而被打开以在信号传送时钟电路的第一操作阶段中实现通过第一级的输入数据的传送。 动态锁存器具有耦合到第一电路的输出的数据输入，并且响应于施加到第一电路的相同或不同的脉冲时钟信号的第二电平而被打开，以施加到第一电路施加的第二电平，以实现由第一电路产生的数据的传输 在第二阶段中，至少一个后续电路，在信号传送时钟电路的第二个连续的操作阶段中，后续电路被一个时钟信号打开和关闭，该时钟信号的相位和频率特性与 动态锁存器。 在信号传输时钟电路中使用的动态锁存时钟方法特别适用于任何传统的静态锁存电路，例如CMOS静态锁存电路，尽管不限于此，以最小化最小延迟竞争违规并实现偏斜容限操作。
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19.发明授权Global clock self-timed circuit with self-terminating precharge for high frequency applications 失效全自动时钟自适应电路，具有自适应高频应用的预充电功能公开(公告)号：US06531897B1
公开(公告)日：2003-03-11
申请号：US09608389
申请日：2000-06-30
IPC分类号： H03K19096
CPC分类号： H03K19/0966
摘要： A global clock self-timed circuit initiates a precharge pulse in response to which a domino node is precharged. A self-terminating precharge circuit coupled to the global clock self-timed circuit and the domino node terminates the precharge pulse after the domino node has been precharged.
摘要翻译： 全局时钟自定时电路启动预充电脉冲，响应于预充电脉冲。 耦合到全局时钟自定时电路和多米诺骨架的自终端预充电电路在多米诺骨牌节点预充电之后终止预充电脉冲。
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20.发明授权Processor having execution core sections operating at different clock rates 有权具有执行核心部分以不同时钟速率工作的处理器公开(公告)号：US06487675B2
公开(公告)日：2002-11-26
申请号：US09775383
申请日：2001-02-02
IPC分类号： G06F104
CPC分类号： G06F1/02 , G06F1/06 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译： 一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。 第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。 处理器还可以包括可能仍然比第一执行核心部分慢的I / O环。 可选地，第一执行核心部分可以包括其时钟速率在第一执行核心部分和第二执行核心部分之间的第三执行核心部分。 可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。
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