公开(公告)号：US07872502B2

公开(公告)日：2011-01-18

申请号：US11484961

申请日：2006-07-12

Applicant: Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

Inventor： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

IPC: H03K19/094

CPC classification number: H03K19/007 ,  G06F11/1076 ,  H03K19/00315

Abstract: One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

Abstract translation: 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。

公开(公告)号：US20080237886A1

公开(公告)日：2008-10-02

申请号：US11729228

申请日：2007-03-28

Applicant: Wei Wu ,  R. Stanley Williams ,  Warren Robinett ,  Gregory S. Snider ,  Zhaoning Yu ,  Shih-Yuan Wang ,  Duncan Stewart

Inventor： Wei Wu ,  R. Stanley Williams ,  Warren Robinett ,  Gregory S. Snider ,  Zhaoning Yu ,  Shih-Yuan Wang ,  Duncan Stewart

IPC: H01L23/48

CPC classification number: H01L27/101 ,  B82Y10/00 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0033 ,  G11C2213/71 ,  G11C2213/79 ,  G11C2213/81 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

Abstract: Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.

Abstract translation: 本发明的各种实施例涉及三维横杆阵列。 在本发明的一个方面，三维交叉开关阵列包括多个交叉开关阵列，第一解复用器，第二解复用器和第三解复用器。 每个横杆阵列包括第一纳米线层，覆盖第一纳米线层的第二纳米线层和覆盖第二纳米线层的第三层纳米线。 第一解复用器被配置为寻址每个交叉列阵列的纳米线的第一层中的纳米线，第二解复用器被配置为寻址每个交叉列阵列的第二纳米线层中的纳米线，并且第三解复用器被配置为向 纳米线在每个交叉列阵列的第三层纳米线中。

公开(公告)号：US20080094629A1

公开(公告)日：2008-04-24

申请号：US11584461

申请日：2006-10-20

Applicant: Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

Inventor： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

IPC: G01B11/00

CPC classification number: G03F9/7049 ,  G03F9/7003

Abstract: Lithography tools and substrates are aligned by generating geometric interference patterns using optical gratings associated with the lithography tools and substrates. In some embodiments, the relative position between a substrate and lithography tool is adjusted to cause at least one geometric shape to have a predetermined size or shape representing acceptable alignment. In additional embodiments, Moiré patterns that exhibit varying sensitivity are used to align substrates and lithography tools. Furthermore, lithography tools and substrates are aligned by causing radiation to interact with optical gratings positioned between the lithography tools and substrates. Lithography tools include an optical grating configured to generate a portion of an interference pattern that exhibits a sensitivity that increases as the relative position between the tools and a substrate moves towards a predetermined alignment position.

Abstract translation: 通过使用与光刻工具和衬底相关的光栅产生几何干涉图案来对准平版印刷工具和衬底。 在一些实施例中，调整衬底和光刻工具之间的相对位置以使得至少一个几何形状具有表示可接受对准的预定尺寸或形状。 在另外的实施例中，使用呈现不同灵敏度的莫尔图案来对准衬底和光刻工具。 此外，光刻工具和衬底通过使辐射与位于光刻工具和衬底之间的光栅相互作用来对准。 平版印刷工具包括光栅，其被配置为产生表现出灵敏度的一部分干涉图案，该灵敏度随着工具和基板之间的相对位置朝向预定对准位置移动而增加。

公开(公告)号：US20080013393A1

公开(公告)日：2008-01-17

申请号：US11484961

申请日：2006-07-12

Applicant: Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

Inventor： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

IPC: G11C17/18

CPC classification number: H03K19/007 ,  G06F11/1076 ,  H03K19/00315

Abstract: One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

Abstract translation: 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。

公开(公告)号：US08773167B2

公开(公告)日：2014-07-08

申请号：US13561978

申请日：2012-07-30

Applicant: Warren Robinett ,  R. Stanley Williams

Inventor： Warren Robinett ,  R. Stanley Williams

IPC: H03K19/00 ,  G11C11/00

CPC classification number: H03K19/173 ,  G11C13/0007 ,  H03K19/17712 ,  H03K19/17728

Abstract: Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor.

Abstract translation: 使用忆阻器实现逻辑可以包括在逻辑单元中具有至少三个忆阻器和偏置电阻器的电路。 至少三个忆阻器中的一个是逻辑单元内的输出忆阻器，至少三个忆阻器的其他忆阻器是输入忆阻器。 至少三个忆阻器和偏置电阻器中的每一个电连接到电压源，其中施加到至少三个忆阻器中的每一个的每个电压和至少三个忆阻器的偏置电阻器和电阻状态确定输出忆阻器的电阻状态 。

公开(公告)号：US20110057683A1

公开(公告)日：2011-03-10

申请号：US12947585

申请日：2010-11-16

Applicant: Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

Inventor： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

IPC: H03K19/003

CPC classification number: H03K19/007 ,  G06F11/1076 ,  H03K19/00315

Abstract: One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

Abstract translation: 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。

公开(公告)号：US20100197117A1

公开(公告)日：2010-08-05

申请号：US12761300

申请日：2010-04-15

Applicant: Zhiyong Li ,  Warren Robinett

Inventor： Zhiyong Li ,  Warren Robinett

IPC: H01L21/768 ,  H01L23/525 ,  H01L21/02

CPC classification number: G11C5/06 ,  B82B1/00 ,  B82B3/00 ,  B82Y10/00 ,  B82Y40/00 ,  G11C5/12 ,  G11C2213/81 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L51/0595 ,  Y10S977/762 ,  Y10S977/94

Abstract: Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state. Other embodiments of the present invention are directed to a nanowire structure including a mixed-scale interface.

Abstract translation: 本发明的某些实施例涉及一种编程纳米线至导电元件电连接的方法。 该方法包括：提供包括多个覆盖有第一纳米线层的导电元件的衬底，至少一些导电元件通过单独的开关结与多于一个的纳米线电耦合，每个开关结配置在 低电导状态或高电导状态; 以及将所述开关结的一部分从所述低电导状态切换到所述高电导状态或所述高电导状态至所述低电导状态，使得所述第一纳米线层的单个纳米线电耦合到不同的导电元件 使用在高电导状态下配置的不同的一个开关结的导电元件的数量。 本发明的其它实施方案涉及包括混合规模界面的纳米线结构。

公开(公告)号：US07612882B2

公开(公告)日：2009-11-03

申请号：US11584461

申请日：2006-10-20

Applicant: Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

Inventor： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

IPC: G01B11/00 ,  G01B11/14

CPC classification number: G03F9/7049 ,  G03F9/7003

Abstract: Lithography tools and substrates are aligned by generating geometric interference patterns using optical gratings associated with the lithography tools and substrates. In some embodiments, the relative position between a substrate and lithography tool is adjusted to cause at least one geometric shape to have a predetermined size or shape representing acceptable alignment. In additional embodiments, Moiré patterns that exhibit varying sensitivity are used to align substrates and lithography tools. Furthermore, lithography tools and substrates are aligned by causing radiation to interact with optical gratings positioned between the lithography tools and substrates. Lithography tools include an optical grating configured to generate a portion of an interference pattern that exhibits a sensitivity that increases as the relative position between the tools and a substrate moves towards a predetermined alignment position.

Abstract translation: 通过使用与光刻工具和衬底相关的光栅产生几何干涉图案来对准平版印刷工具和衬底。 在一些实施例中，调整衬底和光刻工具之间的相对位置以使得至少一个几何形状具有表示可接受对准的预定尺寸或形状。 在另外的实施例中，使用呈现不同灵敏度的莫尔图案来对准衬底和光刻工具。 此外，光刻工具和衬底通过使辐射与位于光刻工具和衬底之间的光栅相互作用来对准。 平版印刷工具包括光栅，其被配置为产生表现出灵敏度的一部分干涉图案，该灵敏度随着工具和基板之间的相对位置朝向预定对准位置移动而增加。

公开(公告)号：US20080099929A1

公开(公告)日：2008-05-01

申请号：US11590492

申请日：2006-10-30

Applicant: Zhiyong Li ,  Warren Robinett

Inventor： Zhiyong Li ,  Warren Robinett

IPC: H01L23/52 ,  H01L21/44

CPC classification number: G11C5/06 ,  B82B1/00 ,  B82B3/00 ,  B82Y10/00 ,  B82Y40/00 ,  G11C5/12 ,  G11C2213/81 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L51/0595 ,  Y10S977/762 ,  Y10S977/94

Abstract: Certain embodiments of the present invention are directed to a method of fabricating a mixed-scale electronic interface. A substrate is provided with a first set of conductive elements. A first layer of nanowires may be formed over the first set of conductive elements. A number of channels may be formed, with each of the channels extending diagonally through a number of the nanowires of the first layer. A number of pads may be formed, each of which is electrically interconnected with an underlying conductive element of the first set of conductive elements and one or more adjacent nanowires of the first layer of nanowires. The pads and corresponding electrically interconnected nanowires define a number of pad-interconnected-nanowire-units. Additional embodiments are directed to a method of forming a nanoimprinting mold and a method of selectively programming nanowire-to-conductive element electrical connections.

Abstract translation: 本发明的某些实施例涉及一种制造混合比例电子接口的方法。 衬底设置有第一组导电元件。 可以在第一组导电元件上形成第一层纳米线。 可以形成多个通道，其中每个通道对角地延伸穿过第一层的多个纳米线。 可以形成多个焊盘，每个焊盘与第一组导电元件的下面的导电元件和第一纳米线层的一个或多个相邻的纳米线电互连。 焊盘和相应的电互连纳米线限定了多个衬垫互连的纳米线单元。 另外的实施例涉及形成纳米压印模具的方法和选择性地编程纳米线至导电元件电连接的方法。

公开(公告)号：US20080089110A1

公开(公告)日：2008-04-17

申请号：US11582208

申请日：2006-10-16

Applicant: Warren Robinett ,  Philip J. Kuekes

Inventor： Warren Robinett ,  Philip J. Kuekes

IPC: G11C11/00

CPC classification number: G11C13/02 ,  B82Y10/00 ,  G06F11/1008 ,  G06F11/1076 ,  G11C11/54 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2013/009 ,  G11C2213/16 ,  G11C2213/77 ,  G11C2213/81

Abstract: Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system comprises a first layer of microscale signal lines, a second layer of microscale signal lines, a first layer of nanowires configured so that each first layer nanowire overlaps each first layer microscale signal line, and a second layer of nanowires configured so that each second layer nanowire overlaps each second layer microscale signal line and overlaps each first layer nanowire. The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires to first layer microscale signal lines and to selectively connect second layer nanowires to second layer microscale signal lines. The crossbar-memory system also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire at each crossbar intersection.

Abstract translation: 本发明的各种实施例涉及交叉存储器系统，用于将信息写入和读取存储在这样的系统中的信息的方法。 在本发明的一个实施例中，交叉开关存储器系统包括微米级信号线的第一层，微米级信号线的第二层，被配置为使得每个第一层纳米线与每个第一层微米信号线重叠的第一纳米线层， 以及第二层纳米线，其被配置为使得每个第二层纳米线与每个第二层微米信号线重叠并且与每个第一层纳米线重叠。 交叉开关存储器系统包括非线性隧道电阻器，其被配置为选择性地将第一层纳米线连接到第一层微型信号线并且选择性地将第二层纳米线连接到第二层微量信号线。 交叉开关存储器系统还包括非线性隧道迟滞电阻器，其被配置为在每个交叉点交叉处将每个第一层纳米线连接到每个第二层纳米线。