公开(公告)号：US20060124982A1

公开(公告)日：2006-06-15

申请号：US10905094

申请日：2004-12-15

Applicant: Herbert Ho ,  John Barth ,  Ramachandra Divakaruni ,  Wayne Ellis ,  Johnathan Faltermeier ,  Brent Anderson ,  Subramanian Iyer ,  Deok-Kee Kim ,  Randy Mann ,  Paul Parries

Inventor： Herbert Ho ,  John Barth ,  Ramachandra Divakaruni ,  Wayne Ellis ,  Johnathan Faltermeier ,  Brent Anderson ,  Subramanian Iyer ,  Deok-Kee Kim ,  Randy Mann ,  Paul Parries

IPC: H01L29/94 ,  H01L27/108

CPC classification number: H01L27/0805 ,  H01L29/66181 ,  H01L29/945

Abstract: A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

Abstract translation: 一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。 在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

公开(公告)号：US20050255387A1

公开(公告)日：2005-11-17

申请号：US10846275

申请日：2004-05-14

Applicant: Shahid Butt ,  Scott Bukofsky ,  Ramachandra Divakaruni ,  Carl Radens ,  Wayne Ellis

Inventor： Shahid Butt ,  Scott Bukofsky ,  Ramachandra Divakaruni ,  Carl Radens ,  Wayne Ellis

IPC: G03C5/00 ,  G03F1/00 ,  G03F9/00 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/02

CPC classification number: G03F1/30 ,  H01L21/3083 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10882

Abstract: An active area pattern is formed atop a deep trench pattern with a single exposure using an alternative phase-shift mask. To prevent adjacent spaces of opposite phase from intersecting one another at the ends of substantially opaque features of the active area pattern, one or more connectors are used to connect the ends of the substantially opaque patterns. Trench regions of the deep trench pattern are arranged such that the conduction path of the connectors are interrupted and prevent the lines from shorting to one another. Alternatively, a bit line pattern or a word line pattern having a lines and spaces array and a support region are printed with a single exposure using an alternating phase-shift mask. At one end of the array region, lines having a respective phase shift extend into the support region, and lines of the opposite phase shift are terminated. At the opposite end of the array, the lines that have the opposite phase shift extend into the support region, and the lines of having the respective phase shift are terminated.

Abstract translation: 使用替代的相移掩模，通过单次曝光在深沟槽图案之上形成有源区域图案。 为了防止相对相位的相邻空间在有源区域图案的基本不透明特征的端部彼此相交，使用一个或多个连接器来连接基本不透明图案的端部。 深沟槽图案的沟槽区域布置成使得连接器的传导路径被中断，并且防止线路彼此短路。 或者，使用交替相移掩模以单次曝光印刷具有线和间隔阵列的位线图案或字线图案和支撑区域。 在阵列区域的一端，具有相应相移的线延伸到支撑区域，并且相反相移的线路终止。 在阵列的相对端，具有相反相移的线延伸到支撑区域中，并且具有相应相移的线路终止。

公开(公告)号：US06320803B1

公开(公告)日：2001-11-20

申请号：US09533226

申请日：2000-03-23

Applicant: Martin Gall ,  Wayne Ellis ,  Shinji Miyamoto ,  Masahiro Yoshihara

Inventor： Martin Gall ,  Wayne Ellis ,  Shinji Miyamoto ,  Masahiro Yoshihara

IPC: G11C700

CPC classification number: G01R31/31724 ,  G01R31/3187 ,  G01R31/31917 ,  G11C29/26

Abstract: There is provided method and apparatus for improving and making more effective the testing of very large scale integrated (VLSI) devices such as a synchronous random access memory (SDRAM), along with improving their performance and their yield in production. The method includes the steps of providing a VLSI device with switching circuitry which permits respective arrays or banks of the device to be tested alone or simultaneously with separate sequences of test mode signals to identify defects, interactions and unwanted limitations in the overall performance of the device; using the information thus obtained to modify the test mode signals and where indicated the design of the device; iterating the previous steps to optimize a test methodology for the device; and using the optimized test methodology during burn-in of production devices. Logic circuitry is added to a VLSI device to facilitate the improved testing capability.

Abstract translation: 提供了用于改进和更有效地测试诸如同步随机存取存储器（SDRAM）的大规模集成（VLSI）设备的方法和装置，同时提高其性能和生产成本。 该方法包括以下步骤：为VLSI设备提供切换电路，其允许单独或同时测试设备的相应阵列或同时测试模式信号的单独序列，以识别设备的整体性能中的缺陷，相互作用和不期望的限制 ; 使用如此获得的信息来修改测试模式信号，并且指示设备的设计; 迭代以前的步骤来优化设备的测试方法; 并在生产设备烧录期间使用优化的测试方法。 逻辑电路被添加到VLSI设备，以便于改进的测试能力。

公开(公告)号：US08710566B2

公开(公告)日：2014-04-29

申请号：US12717776

申请日：2010-03-04

Applicant: Wayne Ellis ,  John Kim

Inventor： Wayne Ellis ,  John Kim

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L27/1052 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/7841

Abstract: Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device. The semiconductor memory device may comprise a substrate comprising an upper layer. The semiconductor memory device may also comprise an array of dummy pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the dummy pillars may extend upward from the upper layer and have a bottom contact that is electrically connected with the upper layer of the substrate. The semiconductor memory device may also comprise an array of active pillars formed on the upper layer of the substrate and arranged in rows and columns. Each of the active pillars may extend upward from the upper layer and have an active first region, an active second region, and an active third region. Each of the active pillars may also be electrically connected with the upper layer of the substrate.

Abstract translation: 公开了用于在半导体存储器件中形成与埋入扩散层的接触的技术。 在一个特定的示例性实施例中，这些技术可以被实现为半导体存储器件。 半导体存储器件可以包括包括上层的衬底。 半导体存储器件还可以包括形成在衬底的上层上并以行和列布置的虚拟柱的阵列。 每个虚拟柱可以从上层向上延伸并且具有与衬底的上层电连接的底部接触。 半导体存储器件还可以包括形成在衬底的上层上并以行和列布置的活性柱的阵列。 每个有源支柱可以从上层向上延伸，并且具有活动的第一区域，活动的第二区域和活动的第三区域。 每个活性柱也可以与衬底的上层电连接。

公开(公告)号：US20070001708A1

公开(公告)日：2007-01-04

申请号：US11531140

申请日：2006-09-12

Applicant: Claude Bertin ,  Wayne Ellis ,  Mark Kellogg ,  William Tonti ,  Jerzy Zalesinski ,  James Leas ,  Wayne Howell

Inventor： Claude Bertin ,  Wayne Ellis ,  Mark Kellogg ,  William Tonti ,  Jerzy Zalesinski ,  James Leas ,  Wayne Howell

IPC: G01R31/26

CPC classification number: G01R31/2867 ,  G11C5/04 ,  G11C29/06 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/56016 ,  G11C29/785 ,  G11C2029/2602 ,  G11C2029/5602 ,  H01L22/22 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.

Abstract translation: 在载体上提供多个半导体器件用于测试或烧录。 然后将载体切割以提供单个芯片上载波部件或多芯片载波部件。 载体用作每个芯片的第一级封装。 因此，载体用于测试和烧录和包装的双重目的。 可以在每个芯片或载体上提供诸如内置自检引擎的引线减少机构，并且连接到载体的触点用于测试和老化步骤。 切割后的最终包装包括至少一个已知的良好的模具，并且可以包括载体上的芯片阵列，例如SIMM或DIMM。 最终的包装也可以是一堆芯片，每个芯片都安装在单独的载体上。 堆叠的载体通过沿着堆叠的侧面安装的基板彼此连接，该基板沿着每个载体的边缘电连接到焊盘一排。

公开(公告)号：US20050009312A1

公开(公告)日：2005-01-13

申请号：US10604112

申请日：2003-06-26

Applicant: Shahid Butt ,  Wayne Ellis ,  John Gabric

Inventor： Shahid Butt ,  Wayne Ellis ,  John Gabric

IPC: H01L29/423 ,  G06F17/50 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/49 ,  H01L29/76

CPC classification number: H01L21/823437 ,  G06F17/5068 ,  H01L27/0207 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device including: a semiconductor substrate having an array of gate conductors, each having a length and a width, comprised of dummy gate conductors and functional gate conductors extending in a widthwise direction, the gate conductors positioned substantially parallel to each other in the widthwise direction and periodically spaced apart a fixed distance in a direction substantially perpendicular to the widthwise direction.

Abstract translation: 一种电子设备，包括：半导体衬底，其具有各自具有长度和宽度的栅极导体阵列，所述栅极导体阵列包括虚拟栅极导体和沿宽度方向延伸的功能栅极导体，所述栅极导体在宽度方向上基本上彼此平行 并且在基本上垂直于宽度方向的方向上周期性地间隔开固定距离。

公开(公告)号：US06670667B2

公开(公告)日：2003-12-30

申请号：US10213061

申请日：2002-08-06

Applicant: Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

Inventor： Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

IPC: H01L27108

CPC classification number: H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4983

Abstract: A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.

公开(公告)号：US06458646B1

公开(公告)日：2002-10-01

申请号：US09608019

申请日：2000-06-30

Applicant: Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

Inventor： Ramachandra Divakaruni ,  Wayne Ellis ,  Jack Mandelman ,  Mary Weybright

IPC: H01L218242

CPC classification number: H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/4983

Abstract: A memory device structure including an array device region having one or more asymmetric gates formed therein, wherein each asymmetric gate comprises a first edge having a substantially vertical sidewall and a second edge having a polysilicon step segment, and a support device region including one or more patterned gate conductors formed therein, wherein each patterned gate conductor in the support device region includes edges having substantially vertical sidewalls. The structure may further include a circuit device region located between the array device region and the support device region, said core device region including one or more patterned gates, each gate including a polysilicon step segment on each side of the gate.

Abstract translation: 一种存储器件结构，包括其中形成有一个或多个非对称栅极的阵列器件区域，其中每个非对称栅极包括具有基本上垂直的侧壁的第一边缘和具有多晶硅台阶段的第二边缘，以及包括一个或多个 形成在其中的图案化栅极导体，其中支撑装置区域中的每个图案化栅极导体包括具有基本垂直侧壁的边缘。 该结构还可以包括位于阵列器件区域和支撑器件区域之间的电路器件区域，所述芯部器件区域包括一个或多个图案化栅极，每个栅极包括在栅极的每一侧上的多晶硅阶梯段。

公开(公告)号：US5421787A

公开(公告)日：1995-06-06

申请号：US947061

申请日：1992-09-18

Applicant: Wayne Ellis

Inventor： Wayne Ellis

IPC: B23Q5/16 ,  F16H9/12 ,  F16H7/08

CPC classification number: B23Q5/162 ,  F16H9/12

Abstract: The invention effects an increase in the range of continuously variable tool speed and torque control for machine tools beyond that conventionally available for operation from single phase alternating current. Interactive operator control of mechanical speed regulation is additively coupled to electrical control of direct current motor drive to reduce or eliminate machine down time needed for performing a series of varied machine operations.

Abstract translation: 本发明对于机械工具的连续可变刀具速度和转矩控制的范围的增加超出了常规可用于单相交流电的操作。 机械速度调节的交互式操作员控制与直流电动机驱动的电气控制相加耦合，以减少或消除执行一系列不同机器操作所需的停机时间。