公开(公告)号：US20110084335A1

公开(公告)日：2011-04-14

申请号：US12614434

申请日：2009-11-08

Applicant: Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

Inventor： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

IPC: H01L27/06 ,  H01L21/8234 ,  H01L23/60

CPC classification number: H01L27/0629 ,  H01L23/60 ,  H01L24/05 ,  H01L27/0255 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.

Abstract translation: 具有漏极电压保护的功率半导体器件包括半导体衬底，至少沟槽栅极晶体管器件和至少沟槽ESD保护器件。 半导体衬底的上表面具有第一沟槽和第二沟槽。 沟槽栅极晶体管器件设置在第一沟槽和半导体衬底中。 沟槽ESD保护器件设置在第二沟槽中，并且包括第一掺杂区，第二掺杂区和第三掺杂区。 第一掺杂区域和第三掺杂区域分别电连接到沟槽栅极晶体管器件的漏极和栅极。

公开(公告)号：US07851310B2

公开(公告)日：2010-12-14

申请号：US12483237

申请日：2009-06-11

Applicant: Li-Cheng Lin ,  Wei-Chieh Lin

Inventor： Li-Cheng Lin ,  Wei-Chieh Lin

IPC: H01L21/338

CPC classification number: H01L29/4236 ,  H01L29/66621 ,  H01L29/78

Abstract: A method for forming semiconductor device, which simultaneously forms a trench MOS transistor device, and an embedded schottky barrier diode (SBD) device in a semiconductor substrate. The embedded SBD device has lower forward voltage drop, which reduces power dissipation. In addition, the voltage bearing ability may be modified easily by virtue of altering the dopant concentration or the width of the voltage bearing dopant region, or the thickness of epitaxial silicon layer. Furthermore, extra cost of purchasing SBD diode may be saved.

Abstract translation: 一种在半导体衬底中同时形成沟槽MOS晶体管器件和嵌入肖特基势垒二极管（SBD）器件的半导体器件的形成方法。 嵌入式SBD器件具有较低的正向压降，从而降低功耗。 此外，由于改变掺杂剂掺杂剂区域的掺杂剂浓度或宽度，或外延硅层的厚度，可以容易地改变电压承载能力。 此外，可以节省购买SBD二极管的额外成本。

公开(公告)号：US20100216290A1

公开(公告)日：2010-08-26

申请号：US12483237

申请日：2009-06-11

Applicant: Li-Cheng Lin ,  Wei-Chieh Lin

Inventor： Li-Cheng Lin ,  Wei-Chieh Lin

IPC: H01L21/336

CPC classification number: H01L29/4236 ,  H01L29/66621 ,  H01L29/78

Abstract: A method for forming semiconductor device, which simultaneously forms a trench MOS transistor device, and an embedded schottky barrier diode (SBD) device in a semiconductor substrate. The embedded SBD device has lower forward voltage drop, which reduces power dissipation. In addition, the voltage bearing ability may be modified easily by virtue of altering the dopant concentration or the width of the voltage bearing dopant region, or the thickness of epitaxial silicon layer. Furthermore, extra cost of purchasing SBD diode may be saved.

公开(公告)号：US08426914B2

公开(公告)日：2013-04-23

申请号：US13013832

申请日：2011-01-26

Applicant: Wei-Chieh Lin

Inventor： Wei-Chieh Lin

IPC: H01L29/00

CPC classification number: H01L23/49562 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823487 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49524 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1087 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/7813 ,  H01L29/7835 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The present invention provides a semiconductor device including a semiconductor substrate having a first conductive type, at least one high-side transistor device and at least one low-side transistor device. The high-side transistor device includes a doped high-side base region having a second conductive type, a doped high-side source region having the first conductive type and a doped drain region having the first conductive type. The doped high-side base region is disposed within the semiconductor substrate, and the doped high-side source region and the doped drain region are disposed within the doped high-side base region. The doped high-side source region is electrically connected to the semiconductor substrate, and the semiconductor substrate is regarded as a drain of the low-side transistor device.

Abstract translation: 本发明提供一种半导体器件，其包括具有第一导电类型的半导体衬底，至少一个高侧晶体管器件和至少一个低侧晶体管器件。 高侧晶体管器件包括具有第二导电类型的掺杂高侧基极区域，具有第一导电类型的掺杂高侧源极区域和具有第一导电类型的掺杂漏极区域。 掺杂的高侧基极区域设置在半导体衬底内，并且掺杂的高侧源极区域和掺杂漏极区域设置在掺杂的高侧基极区域内。 掺杂的高侧源极区域与半导体衬底电连接，半导体衬底被认为是低侧晶体管器件的漏极。

公开(公告)号：US08362529B2

公开(公告)日：2013-01-29

申请号：US12784505

申请日：2010-05-21

Applicant: Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

Inventor： Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

IPC: H01L29/76

CPC classification number: H01L27/06 ,  H01L29/739

Abstract: A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.

Abstract translation: 具有可调输出电容的功率半导体器件包括半导体衬底，其具有限定在其上的第一器件区域和第二器件区域，至少一个设置在第一器件区域中的功率晶体管器件，设置在第二器件区域的半导体衬底中的重掺杂区域 设置在重掺杂区域上的电容器电介质层，设置在半导体衬底的顶表面上并电连接到功率晶体管器件的源极金属层和设置在半导体衬底的底表面上的漏极金属层 。 第二器件中的源极金属层，电容器介质层和重掺杂区形成缓冲电容器。

公开(公告)号：US20120146138A1

公开(公告)日：2012-06-14

申请号：US13070479

申请日：2011-03-24

Applicant: Wei-Chieh Lin

Inventor： Wei-Chieh Lin

IPC: H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: The power device with low parasitic transistor comprises a recessed transistor and a heavily doped region at a side of a source region of the recessed transistor. The conductive type of the heavily doped region is different from that of the source region. In addition, a contact plug contacts the heavily doped region and connects the heavily doped region electrically. A source wire covers and contacts the source region and the contact plug to make the source region and the heavily doped region have the same electrical potential.

Abstract translation: 具有低寄生晶体管的功率器件包括凹陷晶体管和位于凹陷晶体管的源极区一侧的重掺杂区域。 重掺杂区域的导电类型与源极区域的导电类型不同。 此外，接触插塞接触重掺杂区域并电连接重掺杂区域。 源极线覆盖并接触源极区域和接触插塞以使源极区域和重掺杂区域具有相同的电势。

公开(公告)号：US20110291183A1

公开(公告)日：2011-12-01

申请号：US12840283

申请日：2010-07-20

Applicant: Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

Inventor： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jia-Fu Lin ,  Shian-Hau Liao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/66727 ,  H01L29/66734

Abstract: A power semiconductor device having low gate input resistance and a manufacturing method thereof are provided. The power semiconductor device includes a substrate, at least a trench transistor, a conductive layer, a metal contact plug, an insulating layer, an interlayer dielectric, a gate metal layer, and a source metal layer. The metal contact plug can serve as a buried gate metal bus line, and the metal contact plug can pass under the source metal layer and keeps the area of the source metal layer complete. Accordingly, the present invention can provide a lower gate input resistance without dividing the source metal layer, so the source metal layer can have a larger and complete area for the following packaging and bonding process.

Abstract translation: 提供了具有低栅极输入电阻的功率半导体器件及其制造方法。 功率半导体器件包括至少沟槽晶体管，导电层，金属接触插塞，绝缘层，层间电介质，栅极金属层和源极金属层的衬底。 金属接触插头可以用作掩埋栅极金属总线，并且金属接触插塞可以在源极金属层下方通过，并保持源极金属层的面积完整。 因此，本发明可以在不划分源极金属层的情况下提供较低的栅极输入电阻，因此源极金属层可以具有用于随后的封装和接合工艺的更大和完整的面积。

公开(公告)号：US20110215374A1

公开(公告)日：2011-09-08

申请号：US12784505

申请日：2010-05-21

Applicant: Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

Inventor： Wei-Chieh Lin ,  Guo-Liang Yang ,  Shian-Hau Liao

IPC: H01L27/06 ,  H01L29/739 ,  H01L21/336

CPC classification number: H01L27/06 ,  H01L29/739

Abstract: A power semiconductor device having adjustable output capacitance includes a semiconductor substrate having a first device region and a second device region defined thereon, at lest one power transistor device disposed in the first device region, a heavily doped region disposed in the semiconductor substrate of the second device region, a capacitor dielectric layer disposed on the heavily doped region, a source metal layer disposed on a top surface of the semiconductor substrate and electrically connected to the power transistor device, and a drain metal layer disposed on a bottom surface of the semiconductor substrate. The source metal layer in the second device, the capacitor dielectric layer and the heavily doped region form a snubber capacitor.

Abstract translation: 具有可调输出电容的功率半导体器件包括半导体衬底，其具有限定在其上的第一器件区域和第二器件区域，至少一个设置在第一器件区域中的功率晶体管器件，设置在第二器件区域的半导体衬底中的重掺杂区域 设置在重掺杂区域上的电容器电介质层，设置在半导体衬底的顶表面上并电连接到功率晶体管器件的源极金属层和设置在半导体衬底的底表面上的漏极金属层 。 第二器件中的源极金属层，电容器介质层和重掺杂区形成缓冲电容器。

公开(公告)号：US20110062513A1

公开(公告)日：2011-03-17

申请号：US12616770

申请日：2009-11-11

Applicant: Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

Inventor： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

Abstract: An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer.

Abstract translation: 重叠沟槽栅极半导体器件包括半导体衬底，设置在半导体衬底上的多个浅沟槽，设置在浅沟槽中的第一导电层，分别设置在每个浅沟槽中的多个深沟槽，设置在第二导电层中的第二导电层 深沟槽，源极金属层和栅极金属层。 每个深沟槽在每个浅沟槽下延伸到半导体衬底中。 源极金属层电连接到第二导电层，并且栅极金属层电连接到第一导电层。

公开(公告)号：US20100289075A1

公开(公告)日：2010-11-18

申请号：US12536504

申请日：2009-08-06

Applicant: Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

Inventor： Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/336

CPC classification number: H01L27/0629 ,  H01L29/8725

Abstract: A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

Abstract translation: 具有集成MOSFET和肖特基二极管的半导体器件包括其上限定有MOSFET区和肖特基二极管区的衬底; 形成在所述MOSFET区域中的多个第一沟槽; 以及形成在肖特基二极管区域中的多个第二沟槽。 分别包括形成在第一沟槽的侧壁和底部上的第一绝缘层的第一沟槽和填充第一沟槽的第一导电层用作沟槽MOSFET的沟槽栅极。 第二沟槽分别包括形成在第二沟槽的侧壁和底部上的第二绝缘层和填充第二沟槽的第二导电层。 第二沟槽的深度和宽度大于第一沟槽的深度和宽度; 并且所述第二绝缘层的厚度大于所述第一绝缘层的厚度。