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公开(公告)号：US20230329009A1
公开(公告)日：2023-10-12
申请号：US17715065
申请日：2022-04-07
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Chih-Chao Huang , Ming-Che Lin , Frederick Chen , Han-Huei Hsu
CPC classification number: H01L27/2454 , H01L29/0649 , H01L45/124 , H01L29/7851 , H01L45/16 , H01L29/66795
Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.
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公开(公告)号：US11538525B2
公开(公告)日：2022-12-27
申请号：US17495778
申请日：2021-10-06
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.
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公开(公告)号：US20210175418A1
公开(公告)日：2021-06-10
申请号：US16709863
申请日：2019-12-10
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Bo-Lun Wu , Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
IPC: H01L45/00
Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.
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公开(公告)号：US20250072295A1
公开(公告)日：2025-02-27
申请号：US18945580
申请日：2024-11-13
Applicant: Winbond Electronics Corp.
Inventor： Wen-Chia Ou , Chih-Chao Huang , Min-Chih Wei , Yu-Ting Chen , Chi-Ching Liu
Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.
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公开(公告)号：US20250072008A1
公开(公告)日：2025-02-27
申请号：US18939533
申请日：2024-11-07
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Chih-Chao Huang , Ming-Che Lin , Frederick Chen , Han-Huei Hsu
Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.
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Patent Agency Ranking
公开(公告)号：US12193337B2
公开(公告)日：2025-01-07
申请号：US16991055
申请日：2020-08-12
Applicant: Winbond Electronics Corp.
Inventor： Wen-Chia Ou , Chih-Chao Huang , Min-Chih Wei , Yu-Ting Chen , Chi-Ching Liu
Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.
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公开(公告)号：US20230129196A1
公开(公告)日：2023-04-27
申请号：US18087802
申请日：2022-12-22
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Yu-Ting Chen , Chang-Tsung Pai , Shun-Li Lan , Yen-De Lee , Chih-Jung Ni
IPC: H01L21/768 , H10B99/00
Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.
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公开(公告)号：US20220344283A1
公开(公告)日：2022-10-27
申请号：US17586654
申请日：2022-01-27
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Hsiu-Pin Chen , Sung-Ying Wen , Tso-Hua Hung , Yu-An Chen , Ming-Che Lin
IPC: H01L23/00 , H01L23/544 , H01L23/532
Abstract: A semiconductor structure serves to generate a physical unclonable function (PUF) code. The semiconductor structure includes a metal layer, N Titanium (Ti) structures, and N Titanium Nitride (Ti-N) structures, where N is a positive integer. The metal layer forms N metal structures. The Ti structures are respectively formed on one end of each metal structure. The Ti-N structures are respectively formed on top of the Ti structures. The metal structures and the corresponding Ti structures and the corresponding Ti-N structures respectively form a plurality of pillars. The pillars respectively provide a plurality of resistance values, and the resistance values serve to generate the PUF code.
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公开(公告)号：US11152566B2
公开(公告)日：2021-10-19
申请号：US16709863
申请日：2019-12-10
Applicant: Winbond Electronics Corp.
Inventor： Po-Yen Hsu , Bo-Lun Wu , Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
IPC: H01L45/00
Abstract: A resistive random access memory including first and second electrodes, a resistance variable layer, first and second metal layers and a resistance stabilizing layer is provided. The second electrode is disposed on the first electrode. The resistance variable layer is disposed between the first and second electrodes. The first metal layer is disposed between the resistance variable layer and the second electrode. The second metal layer is disposed between the first metal layer and the second electrode. The resistance stabilizing layer is disposed between the first and second metal layers. The oxygen content of the resistance variable layer is higher than that of the first metal layer, the oxygen content of the first metal layer is higher than that of the resistance stabilizing layer, the oxygen content of the resistance stabilizing layer is higher than that of the second metal layer.
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公开(公告)号：US20210287934A1
公开(公告)日：2021-09-16
申请号：US16817572
申请日：2020-03-12
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Yu-Ting Chen , Chang-Tsung Pai , Shun-Li Lan , Yen-De Lee , Chih-Jung Ni
IPC: H01L21/768 , H01L21/8239
Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.
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