公开(公告)号：US11212072B1

公开(公告)日：2021-12-28

申请号：US17130991

申请日：2020-12-22

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini

IPC: H04L7/033 ,  H04L7/00

Abstract: A circuit for processing a data stream is described. The circuit comprises a burst phase detector configured to receive a data input signal; a clocking circuit coupled to the burst phase detector, wherein the clocking circuit is configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal; and a programmable clock generator configured to receive a plurality of clock signals; wherein a selected clock signal of the plurality of clock signals is generated by the programmable clock generator and provided to the burst phase detector and the clocking circuit.

公开(公告)号：US09331724B2

公开(公告)日：2016-05-03

申请号：US14486820

申请日：2014-09-15

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Giovanni Guasti

IPC: G06F3/00 ,  H04B1/04 ,  G06F1/10 ,  G06F5/06 ,  G11C7/22 ,  H04L25/05

CPC classification number: H04B1/0475 ,  G06F1/10 ,  G06F5/06 ,  G06F13/4018 ,  G06F13/423 ,  G11C7/22 ,  G11C7/222 ,  H04L25/05

Abstract: In a method relating generally to starting a plurality of transmitters, a sequence is initiated for each of the plurality of transmitters having corresponding data buffers. Latency is set for each of the data buffers responsive to execution of the sequence. The sequence includes: obtaining a read address associated with a read clock signal; obtaining a write address associated with a write clock signal; determining a difference between the read address and the write address; asserting a flag signal associated with the difference; and adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers.

Abstract translation: 在一般涉及启动多个发射机的方法中，针对具有相应数据缓冲器的多个发射机中的每一个启动序列。 响应于序列的执行，为每个数据缓冲区设置延迟。 该序列包括：获得与读取时钟信号相关联的读取地址; 获得与写入时钟信号相关联的写入地址; 确定读取地址和写入地址之间的差异; 断言与差异相关联的标志信号; 并且调整读取时钟信号以改变差异以定位标志信号的状态位置的变化，以设置数据缓冲器的数据缓冲器的等待时间。

公开(公告)号：US09130807B1

公开(公告)日：2015-09-08

申请号：US14321563

申请日：2014-07-01

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini

IPC: H04L27/22 ,  H04L1/20

CPC classification number: H04L1/20 ,  H04L1/205 ,  H04L7/0041 ,  H04L7/0331

Abstract: A data recovery unit (DRU) includes: an oscillator; a phase detector unit configured to receive a reference phase and to receive input data through N wires, where N is an integer, to compare the reference phase with the input data to obtain phase errors, and to determine an average of the phase errors; a subtractor to subtract an output of the oscillator from the average of the phase errors to obtain an unbiased phase error; a delay unit to receive the input data; and a sample selector configured to receive an output from the delay unit and the output of the oscillator, and to output recovered data.

Abstract translation: 数据恢复单元（DRU）包括：振荡器; 相位检测器单元，被配置为接收参考相位并且通过N条线接收输入数据，其中N是整数，以将参考相位与输入数据进行比较以获得相位误差，并确定相位误差的平均值; 减法器，从相位误差的平均值中减去振荡器的输出，以获得无偏相位误差; 延迟单元，用于接收输入数据; 以及采样选择器，被配置为接收来自延迟单元的输出和振荡器的输出，并输出恢复的数据。

公开(公告)号：US08958513B1

公开(公告)日：2015-02-17

申请号：US13837864

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Martin J. Kellermann

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0337 ,  H03L7/104 ,  H04L7/0338 ,  H04L7/046 ,  H04L7/10

Abstract: A device and method for clock and data recovery are disclosed. For example, an integrated circuit comprises a first branch for recovering a clock signal from an input signal. The first branch includes a phase and frequency detector for detecting a phase and a frequency of the clock signal and a numerically controlled oscillator that is controlled by the phase and the frequency of the clock signal from the phase and frequency detector. The integrated circuit also includes a second branch for recovering a data signal from the input signal. The second branch includes a pre-settable numerically controlled oscillator that is pre-settable with the phase and the frequency of the clock signal from the numerically controlled oscillator. The second branch also includes a sample selector that is controlled by the pre-settable numerically controlled oscillator for recovering the data signal.

Abstract translation: 公开了一种用于时钟和数据恢复的装置和方法。 例如，集成电路包括用于从输入信号恢复时钟信号的第一分支。 第一分支包括用于检测时钟信号的相位和频率的相位和频率检测器以及由相位和频率检测器的时钟信号的相位和频率控制的数控振荡器。 集成电路还包括用于从输入信号中恢复数据信号的第二分支。 第二分支包括一个可预置的数控振荡器，可以用来自数控振荡器的时钟信号的相位和频率进行预设。 第二分支还包括由可预先设定的数控振荡器控制的采样选择器，用于恢复数据信号。

公开(公告)号：US11705910B1

公开(公告)日：2023-07-18

申请号：US17569395

申请日：2022-01-05

Applicant: XILINX, INC.

Inventor： Paolo Novellini

IPC: H03L7/081 ,  G06F13/42 ,  H03K19/21 ,  H03L7/08

CPC classification number: H03L7/0812 ,  G06F13/423 ,  H03K19/21 ,  H03L7/0807

Abstract: Methods and apparatus for quickly changing line rates in PCIe analyzers without resetting the receivers. One example circuit for multi-rate reception generally includes: a receiver having a data input, a data output, and a clock input configured to receive a clock signal from a clock generator, the receiver being configured to switch between receiving data at a first data rate and at least one second data rate and to sample data according to the first data rate, wherein the first data rate is higher than the at least one second data rate; a phase detector having an input coupled to the data output of the receiver; and a filter having an input coupled to an output of the phase detector and having an output configured to effectively control a phase of the sampling by the receiver when the data is at the at least one second data rate.

公开(公告)号：US10547317B1

公开(公告)日：2020-01-28

申请号：US16458859

申请日：2019-07-01

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  David F. Taylor ,  Alastair J. Richardson

IPC: H03L7/085 ,  H04B1/08 ,  H03L7/099

Abstract: A device includes a physical medium attachment (PMA), a physical coding sublayer (PCS), a phase detector, and an oscillator. The PMA receives data at a first speed and overclocks the received data to a second speed, wherein the second speed is higher than the first speed. The PCS receives the data at the second speed. The phase detector receives another data from the PCS wherein the another data is based on the received data at the second speed or the phase detector is configured to receive the data at the second speed directly from the PMA. The phase detector adjusts a phase based on bit transitions. The oscillator is coupled to the phase detector and generates a reference clock signal wherein a phase of the reference clock is adjusted by the phase detector. The oscillator clocks the PMA based on the adjusted clock.

公开(公告)号：US10348312B1

公开(公告)日：2019-07-09

申请号：US15993508

申请日：2018-05-30

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Antonello Di Fresco

IPC: H03L7/081 ,  H03L7/08 ,  H03L7/091 ,  H04L1/20 ,  G11C7/22 ,  H04L7/033

Abstract: A circuit for receiving data is described. The circuit comprises a phase detector circuit comprising a detector having a first input configured to receive a sum of an oscillator phase and a phase error, and a second input coupled to an output of a first sample selector; a second sample selector having an input coupled to receive the input data and generate output data; and an eye detection circuit comprising a third sample selector having an input coupled to receive the input data and a comparator for comparing outputs of the second sample selector and the third sample selector to determine how much an eye is open for a plurality of channels. A method of implementing a receiver is also described.

公开(公告)号：US09992049B1

公开(公告)日：2018-06-05

申请号：US15186006

申请日：2016-06-17

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini

IPC: H04L7/00 ,  H04L27/152

CPC classification number: H04L27/152 ,  H04L7/0079

Abstract: A receiver for processing a data stream includes: a bursty phase detector having a first voltage-controlled oscillator configured to provide a first VCO phase, a signal stream detector configured to provide a data stream phase and a data stream detect signal, and a delay component configured to receive the data stream; a clocking circuit coupled to receive an output of the delay component, the data stream phase, and the data stream detect signal, the clocking circuit configured to provide a second VCO phase at an output of the clocking circuit, wherein the clocking circuit is configured to operate based on a fractional relationship between a reference clock frequency and an output frequency; and a data sample selector with a first input coupled to the output of the delay component, and a second input coupled to the output of the clocking circuit.

公开(公告)号：US20160080008A1

公开(公告)日：2016-03-17

申请号：US14486820

申请日：2014-09-15

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  Giovanni Guasti

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  G06F1/10 ,  G06F5/06 ,  G06F13/4018 ,  G06F13/423 ,  G11C7/22 ,  G11C7/222 ,  H04L25/05

Abstract: In a method relating generally to starting a plurality of transmitters, a sequence is initiated for each of the plurality of transmitters having corresponding data buffers. Latency is set for each of the data buffers responsive to execution of the sequence. The sequence includes: obtaining a read address associated with a read clock signal; obtaining a write address associated with a write clock signal; determining a difference between the read address and the write address; asserting a flag signal associated with the difference; and adjusting the read clock signal to change the difference to locate a change of state location for the flag signal to set the latency for a data buffer of the data buffers.

Abstract translation: 在一般涉及启动多个发射机的方法中，针对具有相应数据缓冲器的多个发射机中的每一个启动序列。 响应于序列的执行，为每个数据缓冲区设置延迟。 该序列包括：获得与读取时钟信号相关联的读取地址; 获得与写入时钟信号相关联的写入地址; 确定读取地址和写入地址之间的差异; 断言与差异相关联的标志信号; 并且调整读取时钟信号以改变差异以定位标志信号的状态位置的变化，以设置数据缓冲器的数据缓冲器的等待时间。