公开(公告)号：US06510095B1

公开(公告)日：2003-01-21

申请号：US10073231

申请日：2002-02-13

申请人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

发明人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2227

摘要： A command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A data input/output circuit starts an output of read data and an input of write data in synchronization with the edges of the clock signal which are set in response to reception timing of the command signal. Since the command signal can be received in synchronization with both edges of the clock signal, it is possible to halve a clock cycle when a reception rate is the same as that of the conventional art. As a result of this, in a system on which the semiconductor memory device is mounted, it is possible to halve the frequency of a system clock and to reduce power consumption of a clock synchronization circuit in the system, without reducing a data input/output rate for the semiconductor memory device.

摘要翻译： 命令接收器电路与时钟信号的上升沿或下降沿同步地接收命令信号。 数据输入/输出电路与响应命令信号的接收定时而设置的时钟信号的边沿同步地开始读取数据的输出和写入数据的输入。 由于可以与时钟信号的两个边沿同步地接收命令信号，所以当接收速率与传统技术的接收速率相同时，可以将时钟周期减半。 结果，在安装了半导体存储器件的系统中，可以将系统时钟的频率减半，并且可以降低系统中时钟同步电路的功耗，而不减少数据输入/输出 速率为半导体存储器件。

公开(公告)号：US06509763B2

公开(公告)日：2003-01-21

申请号：US10162565

申请日：2002-06-06

申请人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Miki Yanagawa

发明人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Miki Yanagawa

IPC分类号： G01R1900

CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

公开(公告)号：US06272069B1

公开(公告)日：2001-08-07

申请号：US09764446

申请日：2001-01-19

申请人： Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Masao Taguchi

发明人： Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Masao Taguchi

IPC分类号： G11C800

摘要： A data signal is output from an output circuit of a first chip and sent to a data input terminal in the second chip via a data lead line based on an output clock in first chip, which is sent to the second chip. And an input circuit in a second chip receives the data signal and transfers it inside in response to a transfer clock that has been generated from the output clock in the first chip. In synchronism with a single reference clock in the first chip, therefore, a data signal can be transferred to the second chip from the first chip at a high speed.

公开(公告)号：US06198689B1

公开(公告)日：2001-03-06

申请号：US09440667

申请日：1999-11-16

申请人： Masafumi Yamazaki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

发明人： Masafumi Yamazaki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22

摘要： The present invention is an integrated circuit device having a self timing control circuit for generating an input loading timing signal whose phase is adjusted with an external clock, where loading of input signals supplied from outside, such as a command input signal, address input signal and data input signal, to internal circuits is forbidden when the self timing control circuit is adjusting phase. And when the self timing control circuit finishes adjusting the phase to a certain degree, the loading operation of an input signal at the input circuit using the input loading timing signal is enabled. To execute such an operation, the input circuit generates an input loading control signal based on a lock-on signal or adjustment signal of the DLL circuit, or based on an input stop cancellation signal, for example. The input circuit controls the stop and restart of loading of the input signal according to this input loading control signal.

摘要翻译： 本发明是一种具有自定时控制电路的集成电路装置，该自定时控制电路用于产生输入负载定时信号，该输入负载定时信号的相位是用外部时钟调整的，其中从外部输入的输入信号如命令输入信号，地址输​​入信号和 数据输入信号，当自定时控制电路正在调整相位时，禁止内部电路。 并且当自定时控制电路在一定程度上完成相位调整时，可以使用输入负载定时信号在输入电路处的输入信号的加载操作。 为了执行这种操作，输入电路基于例如DLL电路的锁定信号或调整信号，或者基于输入停止消除信号，生成输入负载控制信号。 输入电路根据该输入负载控制信号控制输入信号的停止和重新启动。

公开(公告)号：US6078514A

公开(公告)日：2000-06-20

申请号：US61023

申请日：1998-04-16

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Takaaki Suzuki ,  Hiroyoshi Tomita ,  Toshiya Uchida ,  Yasuharu Sato ,  Atsushi Hatakeyama ,  Masato Matsumiya ,  Yasurou Matsuzaki

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Takaaki Suzuki ,  Hiroyoshi Tomita ,  Toshiya Uchida ,  Yasuharu Sato ,  Atsushi Hatakeyama ,  Masato Matsumiya ,  Yasurou Matsuzaki

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H01L21/60 ,  H01L25/00 ,  H01L27/10 ,  H01L25/04 ,  H01L23/36

CPC分类号： H01L23/60 ,  G11C7/1006 ,  G11C7/22 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L24/48 ,  H01L27/0266 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/30105

摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.

摘要翻译： 半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。 所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的 逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是 沿着至少一个存储器芯片的一侧布置。

公开(公告)号：US06774655B2

公开(公告)日：2004-08-10

申请号：US10622472

申请日：2003-07-21

申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

IPC分类号： G01R3102

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

摘要翻译： 公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。 半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。 测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号 并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。 优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。 还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

公开(公告)号：US06621283B1

公开(公告)日：2003-09-16

申请号：US09437221

申请日：1999-11-10

申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

IPC分类号： G01R3102

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

摘要翻译： 公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。 半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。 测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号 并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。 优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。 还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

公开(公告)号：US06194930B1

公开(公告)日：2001-02-27

申请号：US09320847

申请日：1999-05-26

申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Yasuhiro Fujii

发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Yasuhiro Fujii

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  H03L7/0814

摘要： The present invention is a DLL circuit, which delays a first clock, and generates a control clock having a predetermined phase relation with this first clock. The DLL circuit comprises a variable delay circuit for varying the delay of the first clock; a phase comparator for comparing the phases of the first clock against that of a second clock, generated by delaying for a predetermined time the output of the variable delay circuit, and for generating a phase comparison result signal; and a delay control circuit for supplying to the variable delay circuit a delay control signal, which controls this delay quantity in response to the phase comparison result signal. The delay control circuit generates a single delay control signal, which changes by a minimum delay quantity unit a delay quantity of the variable delay circuit in a first operating period of the DLL circuit, and generates a binary delay control signal, which changes by a binary unit a delay quantity of the variable delay circuit in a second operating period that differs from the first operating period of the DLL circuit. A lock-on state can be achieved in a short time, and stable operation is possible.

摘要翻译： 本发明是一种DLL电路，其延迟第一时钟，并产生与该第一时钟具有预定相位关系的控制时钟。 DLL电路包括用于改变第一时钟的延迟的可变延迟电路; 相位比较器，用于通过将可变延迟电路的输出延迟预定时间并产生相位比较结果信号而产生的第一时钟的相位和第二时钟的相位; 以及延迟控制电路，用于向可变延迟电路提供响应于相位比较结果信号来控制该延迟量的延迟控制信号。 延迟控制电路产生单个延迟控制信号，该延迟控制信号在DLL电路的第一操作周期中以最小延迟量单位改变可变延迟电路的延迟量，并产生二进制延迟控制信号，二进制延迟控制信号由二进制 在与DLL电路的第一操作周期不同的第二操作周期中单元可变延迟电路的延迟量。 可以在短时间内实现锁定状态，并且可以稳定地操作。

公开(公告)号：US6133781A

公开(公告)日：2000-10-17

申请号：US349110

申请日：1999-07-08

申请人： Yasuhiro Fujii ,  Yasurou Matsuzaki

发明人： Yasuhiro Fujii ,  Yasurou Matsuzaki

IPC分类号： G11C11/401 ,  G05F3/02 ,  G11C11/407 ,  H01L21/8238 ,  H01L27/092

CPC分类号： G11C11/4097 ,  G11C11/4094 ,  G11C7/12 ,  G11C7/18

摘要： A switch 17 for short-circuiting is connected between the outputs of circuits 15 and 16 each of which outputs a pair of complementary signals .0.S1 and .0.R1. The circuits 15 and 16, and the switch 17 are controlled by a changeover control circuit 18 in response to an input signal .0.A1. To effectively utilizes electric charge which has become unnecessary on a complementary signal line pair, the circuit 18 comprises an edge detecting circuit for providing a pulse to the switch 17 to make it on in response to the edge of the signal .0.A1, and a state control circuit for making the outputs of the circuits 15 and 16 in a high impedance state while the switch 17 being on, and for making the logic states of the signals .0.S1 and .0.R1 completely transit in response to disappearance of the pulse while the switch 17 being off.

摘要翻译： 用于短路的开关17连接在各自输出一对互补信号OS1和OR1的电路15和16的输出之间。 响应于输入信号OA1，电路15和16以及开关17由转换控制电路18控制。 为了有效地利用在互补信号线对上变得不必要的电荷，电路18包括边缘检测电路，用于向开关17提供脉冲以使其响应于信号OA1的边缘而导通，并且状态控制 当开关17接通时使电路15和16的输出处于高阻抗状态，并且用于使信号OS1和OR1的逻辑状态响应于开关17断开时的脉冲消失而完全转变的电路 。

公开(公告)号：US20080285375A1

公开(公告)日：2008-11-20

申请号：US12124765

申请日：2008-05-21

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C8/18 ,  H03L7/00

CPC分类号： G11C7/1057 ,  G06F1/10 ,  G06F5/06 ,  G11C5/063 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/081

摘要： A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment signal from the second clock.

摘要翻译： 模块包括半导体器件，产生第二时钟的相位调整电路，使得从半导体器件输出的相位调整信号和第一时钟具有预定的相位关系，以及设置在半导体器件中的输出电路， 来自第二个时钟的相位调整信号。