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    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    2.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06424199B1

    公开(公告)日：2002-07-23

    申请号：US09978022

    申请日：2001-10-17

    申请人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    发明人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    IPC分类号： H03K3013

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    3.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06225841B1

    公开(公告)日：2001-05-01

    申请号：US09556948

    申请日：2000-04-21

    申请人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    发明人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    IPC分类号： H03B1900

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    4.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
    半导体器件采用互补时钟和信号输入状态检测电路相同

    公开(公告)号：US6104225A

    公开(公告)日：2000-08-15

    申请号：US76810

    申请日：1998-05-13

    申请人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    发明人： Masao Taguchi ,  Yasurou Matsuzaki ,  Miki Yanagawa

    IPC分类号： G11C7/22 ,  H03K5/00 ,  H03K5/135 ,  H03K5/151 ,  H03L7/081 ,  G06F1/04

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180.degree. phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit generates a 1/2 phase shift signal 180.degree. out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    摘要翻译： 公开了一种半导体器件，用于从外部时钟产生彼此互补的第一和第二内部时钟，并且可用于使用互补时钟的系统和内部产生180°相位时钟的系统的系统。 第一时钟输入电路（缓冲器）被提供有第一外部时钟并输出第一内部时钟。 第二时钟输入电路（缓冲器）被提供有与第一外部时钟互补的第二外部时钟并输出第二时钟。 A + E，fra 1/2 + EE相位时钟发生电路产生与第一内部时钟异相180°的+ E，fra 1/2 + EE相移信号。 第二外部时钟状态检测电路判断第二外部时钟是否被输入到第二时钟输入缓冲器。 当第二外部时钟被输入时，开关被操作以产生第二时钟作为第二内部时钟，并且当第二外部时钟未被输入时产生+ E，fra 1/2 + EE相移信号作为第二内部时钟 ，根据第二外部时钟状态检测电路的判断。

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    6.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06333660B2

    公开(公告)日：2001-12-25

    申请号：US09780475

    申请日：2001-02-12

    申请人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

    发明人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

    IPC分类号： H03K3013

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    Semiconductor memory device for operating in synchronization with edge of clock signal
    10.
    发明授权
    Semiconductor memory device for operating in synchronization with edge of clock signal 有权
    用于与时钟信号的边沿同步操作的半导体存储器件

    公开(公告)号：US06510095B1

    公开(公告)日：2003-01-21

    申请号：US10073231

    申请日：2002-02-13

    申请人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

    发明人： Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Masao Taguchi

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C2207/2227

    摘要： A command receiver circuit receives a command signal in synchronization with either a rising edge or a falling edge of a clock signal. A data input/output circuit starts an output of read data and an input of write data in synchronization with the edges of the clock signal which are set in response to reception timing of the command signal. Since the command signal can be received in synchronization with both edges of the clock signal, it is possible to halve a clock cycle when a reception rate is the same as that of the conventional art. As a result of this, in a system on which the semiconductor memory device is mounted, it is possible to halve the frequency of a system clock and to reduce power consumption of a clock synchronization circuit in the system, without reducing a data input/output rate for the semiconductor memory device.

    摘要翻译： 命令接收器电路与时钟信号的上升沿或下降沿同步地接收命令信号。 数据输入/输出电路与响应命令信号的接收定时而设置的时钟信号的边沿同步地开始读取数据的输出和写入数据的输入。 由于可以与时钟信号的两个边沿同步地接收命令信号，所以当接收速率与传统技术的接收速率相同时，可以将时钟周期减半。 结果，在安装了半导体存储器件的系统中，可以将系统时钟的频率减半，并且可以降低系统中时钟同步电路的功耗，而不减少数据输入/输出 速率为半导体存储器件。