公开(公告)号：US06341323B2

公开(公告)日：2002-01-22

申请号：US09777960

申请日：2001-02-07

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F1300

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

摘要翻译： 在数据处理系统中，连接到其系统总线的多个模块被分配有标识符。 当源模块发起对另一个模块的拆分读取访问时，源模块发送访问目标模块的地址和源模块的标识符。 当向源模块发送响应时，目的地模块向其返回响应数据和源模块的标识符。 从目标模块检查标识符，源模块确定作为对发起的访问的响应返回的响应数据。

公开(公告)号：US06219735B1

公开(公告)日：2001-04-17

申请号：US09477666

申请日：2000-01-05

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Hideaki Gemma ,  Tetsuhiko Okada ,  Kazuhiko Komori ,  Koichi Okazawa

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Hideaki Gemma ,  Tetsuhiko Okada ,  Kazuhiko Komori ,  Koichi Okazawa

IPC分类号： G06F1312

CPC分类号： G06F13/364

摘要： An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before. Thus, the address to be transferred can be transferred to the module ready to accept the address, in only one cycle.

摘要翻译： 一种信息处理系统，其中作为执行对模块的读取访问以作为从机操作的主机的模块请求总线仲裁器以提供具有总线主控请求信号的母线的掌握，并且它同时断言最后一个周期 信号，以通知总线仲裁器下一个周期将是主机使用的最后一个周期的事实。 随后，当主机已经使用由总线仲裁器通过总线使用授权信号授予的总线时，它通过在下一个周期中使用总线将地址传送到从机，从而开始读取访问。 读取权限后，主人释放总线主控权。 只有当从站未能接受传送的地址时，它会在地址的传输周期不被接受的两个周期之后重新生成重试请求信号。 在这种情况下，在断言信号的周期之前执行传送两个周期的模块再次执行之前执行的传送。 因此，要传输的地址只能在一个周期内传输到模块准备好接受地址。

公开(公告)号：US5889971A

公开(公告)日：1999-03-30

申请号：US959913

申请日：1997-10-29

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

公开(公告)号：US5483642A

公开(公告)日：1996-01-09

申请号：US311893

申请日：1994-09-26

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

公开(公告)号：US20070106832A1

公开(公告)日：2007-05-10

申请号：US11642511

申请日：2006-12-21

申请人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

发明人： Nobukazu Kondo ,  Seiji Kaneko ,  Koichi Okazawa ,  Hideaki Gemma ,  Tetsuya Mochida ,  Takehisa Hayashi

IPC分类号： G06F13/36

CPC分类号： G06F13/4027 ,  G06F13/36

摘要： In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

公开(公告)号：US06907489B2

公开(公告)日：2005-06-14

申请号：US10787110

申请日：2004-02-27

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

摘要翻译： 与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。 控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。 控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

公开(公告)号：US06748463B1

公开(公告)日：2004-06-08

申请号：US09463599

申请日：2000-06-22

申请人： Masahide Tsuboi ,  Takashi Moriyama ,  Hiroshi Murashima ,  Masumi Terao ,  Michinori Naitoh ,  Koichi Okazawa ,  Masaya Umemura

发明人： Masahide Tsuboi ,  Takashi Moriyama ,  Hiroshi Murashima ,  Masumi Terao ,  Michinori Naitoh ,  Koichi Okazawa ,  Masaya Umemura

IPC分类号： G06F1314

CPC分类号： G06F12/0835

摘要： An information processing apparatus with a hierarchized bus structure having a system bus connected to central processing units and cache memories and an I/O bus connected to I/O devices. In response to a DMA request from the I/O device, a memory controller connected to both buses and to a main memory compares previous snoop addresses stored in a buffer memory of the memory controller with a current address contained in the DMA request to check whether the current DMA request is coincident with the past snoop process. If the comparison indicates a coincident snoop process, a snoop access process request is inhibited to be output to the system bus and cache memory. With this operation, the number of snoop accesses for DMAs to the same block of the cache memory can be reduced and a time during which the system bus is occupied can be shortened, to thereby improve the system performance.

摘要翻译： 具有分级总线结构的信息处理设备，其具有连接到中央处理单元和高速缓冲存储器的系统总线以及连接到I / O设备的I / O总线。 响应于来自I / O设备的DMA请求，连接到总线和主存储器的存储器控​​制器将存储在存储器控制器的缓冲存储器中的先前侦听地址与包含在DMA请求中的当前地址进行比较，以检查是否 当前的DMA请求与过去的窥探过程一致。 如果比较指示一致的窥探过程，则禁止窥探访问过程请求输出到系统总线和高速缓冲存储器。 通过该操作，可以减少DMA到高速缓冲存储器的同一块的窥探访问次数，并且可以缩短系统总线占用的时间，从而提高系统性能。

公开(公告)号：US06546471B1

公开(公告)日：2003-04-08

申请号：US09506810

申请日：2000-02-18

申请人： Toshiaki Tarui ,  Koichi Okazawa ,  Yasuyuki Okada ,  Toru Shonai ,  Toshio Okochi ,  Hideya Akashi

发明人： Toshiaki Tarui ,  Koichi Okazawa ,  Yasuyuki Okada ,  Toru Shonai ,  Toshio Okochi ,  Hideya Akashi

IPC分类号： G06F1314

CPC分类号： G06F12/0826 ,  G06F12/0284 ,  G06F2212/2542

摘要： A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is “0”, a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed.

摘要翻译： 共享存储器多处理器（SMP）具有对包括在特定节点中的主存储器的有效访问以及包括节点的分区的管理。 与包含在节点中的主存储器的每页对应，存储在寄存器中的位指示是否已经从任何其他节点访问了页面。 在比特为“0”的情况下，不发送要发送到其他节点的高速缓存相干命令。 该位在初始化和内存分配时由软件复位，当从任何其他节点访问主存储器的页面时，该位由硬件置1。 在将SMP的内部划分成分区的情况下，将各节点的主存储器划分为本地区域和共享区域，分别分别分配地址。 在每个节点中，共享区域和局部区域的配置信息项存储在寄存器中。 访问共享区域的命令是组播到所有节点，而当访问本地区域时，该命令仅组播到相应分区内的节点。

公开(公告)号：US06519640B2

公开(公告)日：2003-02-11

申请号：US10082185

申请日：2002-02-26

申请人： Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

发明人： Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

IPC分类号： G06F1516

CPC分类号： G06F9/5055 ,  G06F9/5044 ,  G06F2209/5015 ,  H04L29/12047 ,  H04L41/5009 ,  H04L61/15 ,  H04L67/36

摘要： In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

摘要翻译： 在通过网络彼此连接的每个信息处理设备中，布置了其功能和性能被注册到其中的服务质量（QOS）表。 当信息处理设备另外与网络链接时，其QOS表被自动地注册到网络的本地目录，使得代理将QOS表的内容转换成要经由用户界面提供给用户的服务信息 。 由于操作，连接到网络的每个信息处理设备的功能和性能的信息被转换成用户的服务信息。 因此，用户可以更多地直接接收必要的服务。

公开(公告)号：US06378021B1

公开(公告)日：2002-04-23

申请号：US09250155

申请日：1999-02-16

申请人： Koichi Okazawa ,  Toshiaki Tarui ,  Yasuyuki Okada

发明人： Koichi Okazawa ,  Toshiaki Tarui ,  Yasuyuki Okada

IPC分类号： G06F1300

CPC分类号： H04L41/069 ,  G06F15/17375 ,  H04L41/0672 ,  H04L43/0811 ,  H04L49/101 ,  H04L49/201 ,  H04L49/254 ,  H04L49/552

摘要： In an information processing apparatus having a crossbar switch, registers are provided for logical division of a connection of the crossbar switch into a plurality of groups, in order to allow a system to change the group division configuration while the system is in an ordinary operation. As an application of this, in a hot standby system, when a fault occurs in an active partition and the active partition is replaced by a standby partition, the standby partition is allowed to include system resources used by the active partition such as CPU's and memories.

摘要翻译： 在具有交叉开关的信息处理装置中，提供寄存器用于将交叉开关的连接逻辑划分成多个组，以便允许系统在系统处于普通操作时改变组划分配置。 作为应用，在热备份系统中，当在活动分区中发生故障并且活动分区被备用分区替换时，备用分区被允许包括活动分区所使用的系统资源，例如CPU和存储器 。