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35 条记录 (耗时 0.031 秒)

    Wafer edge exposure unit
    11.
    发明授权
    Wafer edge exposure unit 有权
    晶圆边缘曝光单元

    公开(公告)号：US07901854B2

    公开(公告)日：2011-03-08

    申请号：US12437776

    申请日：2009-05-08

    申请人： Po-Chang Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee

    发明人： Po-Chang Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee

    IPC分类号： G03F9/00 ,  G03C5/00 ,  G03B27/32 ,  G03B27/42

    CPC分类号： G03B27/62 ,  G03F7/70425

    摘要： A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.

    摘要翻译： 晶片边缘曝光单元包括用于支撑晶片的卡盘。 卡盘可绕中心轴线旋转。 多个光源以可旋转卡盘的轴线的公共径向距离定位或可移动地定位，每个光源被配置为将曝光光同时引导到晶片的相应边缘部分。

    Line end spacing measurement
    12.
    发明授权
    Line end spacing measurement 有权
    线端距测量

    公开(公告)号：US07393616B2

    公开(公告)日：2008-07-01

    申请号：US11397464

    申请日：2006-04-04

    申请人： Jiann Yuan Huang ,  Anderson Chang ,  Chih-Ming Ke ,  Heng-Jen Lee ,  Chin-Hsiang Lin ,  Tsai-Sheng Gau

    发明人： Jiann Yuan Huang ,  Anderson Chang ,  Chih-Ming Ke ,  Heng-Jen Lee ,  Chin-Hsiang Lin ,  Tsai-Sheng Gau

    IPC分类号： G03F1/00 ,  G03F9/00

    CPC分类号： G03F7/70616

    摘要： A method including: providing collinear first and second lines in a mask layer over a substrate, the first line having at one end a first line end and having a first line body adjacent the first line end, and the second line having at one end a second line end and having a second line body adjacent the second line end; measuring line widths of the first line body and the second line body; locating effective line end positions for the first line end based on the line width of the first line body and for the second line end based on the line width of the second line body; and measuring a distance between the effective line end positions, as an effective line end spacing.

    摘要翻译： 一种方法，包括：在衬底上的掩模层中提供共线的第一和第二线，所述第一线在一端具有第一线端并且具有与所述第一线端相邻的第一线体，并且所述第二线在一端具有 第二线端并且具有与第二线端相邻的第二线体; 测量第一线体和第二线体的线宽; 基于第一线体的线宽度和第二线端基于第二线体的线宽来定位第一线端的有效线端位置; 并测量有效线端位置之间的距离，作为有效线端间距。

    Litho cluster and modulization to enhance productivity
    14.
    发明授权
    Litho cluster and modulization to enhance productivity 有权
    Litho集群和模块化以提高生产力

    公开(公告)号：US08903532B2

    公开(公告)日：2014-12-02

    申请号：US13429921

    申请日：2012-03-26

    申请人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

    发明人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

    IPC分类号： H01L31/18

    CPC分类号： G03F7/30 ,  G03F7/16 ,  G03F7/70991 ,  H01L21/67225 ,  H01L21/67745

    摘要： The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

    摘要翻译： 本公开涉及一种用于半导体工件加工的平版印刷工具装置。 光刻工具装置将光刻工具组合成簇，并且将半导体工件在第一簇中的第一类型的多个光刻工具之间选择性地传输到第二簇中的第二类型的光刻工具。 通过转移组件实现选择性转移，转移组件耦合到识别第一类型的光刻工具中产生的缺陷的缺陷扫描工具。 所公开的平版印刷工具装置还利用共同的结构元件，例如壳体组件和诸如气体和化学品的共享功能元件。 光刻工具装置可以包括被配置成提供这些各种部件的模块化的烘烤，涂覆，曝光和显影单元，以便为给定的光刻制造工艺优化产量和效率。

    Frame cell for shot layout flexibility
    16.
    发明授权
    Frame cell for shot layout flexibility 有权
    帧单元，用于拍摄布局灵活性

    公开(公告)号：US08239788B2

    公开(公告)日：2012-08-07

    申请号：US12537836

    申请日：2009-08-07

    申请人： Chih-Wei Lin ,  Yung-Cheng Chen ,  Heng-Jen Lee

    发明人： Chih-Wei Lin ,  Yung-Cheng Chen ,  Heng-Jen Lee

    IPC分类号： G06F17/50 ,  G03C5/00

    CPC分类号： G03F7/70433

    摘要： A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An initial shot layout having a chip count is established in which a number of shots, each including at least one frame structure segment and at least one chip, are arranged in vertically and horizontally aligned columns and rows. At least one additional shot layout is established in which at least one of a row or column of shots is offset from an adjacent row or column of shots. The initial shot layout is compared to the at least one additional shot layout, and a final shot layout is selected based in part on the total number of shots in the shot layout and has a final chip count that is greater than or equal to the initial chip count.

    摘要翻译： 一种方法包括接收集成电路芯片尺寸并基于芯片尺寸确定帧结构段大小。 帧结构段大小小于芯片大小。 建立具有芯片数量的初始照片布局，其中每个包括至少一个框架结构段和至少一个芯片的镜头排列在垂直和水平排列的列和行中。 建立至少一个额外的镜头布局，其中一列或一列镜头中的至少一个从相邻的行或镜头列偏移。 将初始照片布局与至少一个附加镜头布局进行比较，并且部分地基于镜头布局中的总镜头数量选择最终镜头布局，并且具有大于或等于初始镜头布局的最终​​裁片数量 芯片数量

    COST-EFFECTIVE METHOD FOR EXTREME ULTRAVIOLET (EUV) MASK PRODUCTION
    18.
    发明申请
    COST-EFFECTIVE METHOD FOR EXTREME ULTRAVIOLET (EUV) MASK PRODUCTION 有权
    用于极端超紫外线（EUV）掩蔽生产的成本有效的方法

    公开(公告)号：US20110159410A1

    公开(公告)日：2011-06-30

    申请号：US12650985

    申请日：2009-12-31

    申请人： Chin-Hsiang Lin ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

    发明人： Chin-Hsiang Lin ,  Heng-Jen Lee ,  I-Hsiung Huang ,  Chih-Chiang Tu ,  Chun-Jen Chen ,  Rick Lai

    IPC分类号： G03F1/00 ,  G06F17/50

    CPC分类号： G03F1/24 ,  G03F1/72 ,  G03F1/84

    摘要： The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping.

    摘要翻译： 本公开提供了许多不同的实施例。 示例性方法可以包括提供空白掩模和要在空白掩模上图案化的设计布局，所述设计布局包括临界区域; 检查空白掩模的缺陷并产生与空白掩模相关联的缺陷分布图; 将缺陷分布图映射到设计布局; 进行面膜制作过程; 以及基于所述映射执行掩模缺陷修复处理。

    FRAME CELL FOR SHOT LAYOUT FLEXIBILITY
    19.
    发明申请
    FRAME CELL FOR SHOT LAYOUT FLEXIBILITY 有权
    用于拍摄布局灵活性的框架单元

    公开(公告)号：US20110033787A1

    公开(公告)日：2011-02-10

    申请号：US12537836

    申请日：2009-08-07

    申请人： Chih-Wei Lin ,  Yung-Cheng Chen ,  Heng-Jen Lee

    发明人： Chih-Wei Lin ,  Yung-Cheng Chen ,  Heng-Jen Lee

    IPC分类号： G03F7/20 ,  G06F17/50

    CPC分类号： G03F7/70433

    摘要： A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An initial shot layout having a chip count is established in which a number of shots, each including at least one frame structure segment and at least one chip, are arranged in vertically and horizontally aligned columns and rows. At least one additional shot layout is established in which at least one of a row or column of shots is offset from an adjacent row or column of shots. The initial shot layout is compared to the at least one additional shot layout, and a final shot layout is selected based in part on the total number of shots in the shot layout and has a final chip count that is greater than or equal to the initial chip count.

    摘要翻译： 一种方法包括接收集成电路芯片尺寸并基于芯片尺寸确定帧结构段大小。 帧结构段大小小于芯片大小。 建立具有芯片数量的初始照片布局，其中每个包括至少一个框架结构段和至少一个芯片的镜头排列在垂直和水平排列的列和行中。 建立至少一个额外的镜头布局，其中一列或一列镜头中的至少一个从相邻的行或列的镜头偏移。 将初始照片布局与至少一个附加镜头布局进行比较，并且部分地基于镜头布局中的总镜头数量选择最终镜头布局，并且具有大于或等于初始镜头布局的最终​​裁片数量 芯片数量

    Tool Induced Shift Reduction Determination for Overlay Metrology
    20.
    发明申请
    Tool Induced Shift Reduction Determination for Overlay Metrology 有权
    刀具诱导换位测量用于覆盖计量学

    公开(公告)号：US20130286395A1

    公开(公告)日：2013-10-31

    申请号：US13457832

    申请日：2012-04-27

    申请人： Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

    发明人： Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

    IPC分类号： G01B11/00

    CPC分类号： G01B11/00 ,  G03F7/70633

    摘要： One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.

    摘要翻译： 一个实施例涉及一种用于半导体工件加工的方法。 在该方法中，通过在第一半导体工件上执行TIS测量的基线数量来测量基线工具诱发位移（TIS）。 在确定基线TIS之后，该方法基于在第一后续半导体工件上进行的随后的TIS测量数确定随后的TIS。 随后的TIS测量数量小于TIS测量的基线数量。