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11.发明授权Phase shift mask for extreme ultraviolet lithography and method of fabricating same 有权用于极紫外光刻的相移掩模及其制造方法公开(公告)号：US08765330B2
公开(公告)日：2014-07-01
申请号：US13564198
申请日：2012-08-01
申请人： Chia-Tsung Shih , Pei-Chung Hsu , Shinn-Sheng Yu , Tsiao-Chen Wu , Yen-Cheng Lu , Shu-Hao Chang , Chia-Jen Chen , Hsin-Chang Lee , Anthony Yen
发明人： Chia-Tsung Shih , Pei-Chung Hsu , Shinn-Sheng Yu , Tsiao-Chen Wu , Yen-Cheng Lu , Shu-Hao Chang , Chia-Jen Chen , Hsin-Chang Lee , Anthony Yen
摘要： A mask and method of fabricating same are disclosed. In an example, a mask includes a substrate, a reflective multilayer coating disposed over the substrate, an Ag2O absorber layer disposed over the reflective multilayer coating, and a tantalum-containing absorber layer disposed over the Ag2O absorber layer. The tantalum-containing absorber layer is disposed over the Ag2O absorber layer outside a mask image region of the mask, such that the mask image region of the mask is free of the tantalum-containing absorber layer. In an example, the tantalum-containing absorber layer is disposed over the Ag2O absorber layer adjacent to the mask image region.
摘要翻译： 公开了一种掩模及其制造方法。 在一个示例中，掩模包括基板，设置在基板上的反射多层涂层，设置在反射多层涂层上的Ag 2 O吸收层，以及设置在Ag 2 O吸收层上的含钽吸收层。 含钽吸收层设置在掩模的掩模图像区域外侧的Ag 2 O吸收体层上，使得掩模的掩模图像区域不含含钽吸收层。 在一个实例中，含钽吸收层设置在与掩模图像区域相邻的Ag 2 O吸收层上。
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公开(公告)号：US08709682B2
公开(公告)日：2014-04-29
申请号：US13369061
申请日：2012-02-08
申请人： Chia-Jen Chen , Anthony Yen , Hsin-Chang Lee , Sheng-Chi Chin
发明人： Chia-Jen Chen , Anthony Yen , Hsin-Chang Lee , Sheng-Chi Chin
IPC分类号： G03F1/26
摘要： Provided is a method for reducing phase defects on many different types of semiconductor mask blanks. The method includes receiving a semiconductor mask blank substrate, creating alignment marks on the surface of the substrate, performing an inspection of the surface of the substrate to locate a plurality of surface defects, and repairing the plurality of surface defects on the surface of the substrate. A semiconductor mask is also provided that includes a repaired substrate a multilayer stack comprising a plurality of molybdenum and silicon layers, a capping layer, an absorber layer, and in some instances a photoresist layer.
摘要翻译： 提供了一种用于减少许多不同类型的半导体掩模坯料上的相缺陷的方法。 该方法包括：接收半导体掩模空白基板，在基板的表面上产生对准标记，对基板的表面进行检查以定位多个表面缺陷，以及修复基板表面上的多个表面缺陷 。 还提供了一种半导体掩模，其包括修复的衬底，包括多个钼和硅层的多层叠层，覆盖层，吸收层，并且在一些情况下为光致抗蚀剂层。
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公开(公告)号：US20130219350A1
公开(公告)日：2013-08-22
申请号：US13398923
申请日：2012-02-17
申请人： Hsin-Chang Lee , Chia-Jen Chen , Lee-Chih Yeh , Anthony Yen
发明人： Hsin-Chang Lee , Chia-Jen Chen , Lee-Chih Yeh , Anthony Yen
IPC分类号： G06F17/50
CPC分类号： G03F1/00 , G03F1/20 , G03F1/22 , G03F1/36 , G03F1/42 , G03F1/70 , G06F17/5081 , G06F19/00 , G21K5/00
摘要： A method for reducing layer overlay errors by synchronizing the density of mask material in the frame area across the masks in a set is disclosed. An exemplary method includes creating a mask design database corresponding to a mask and containing a die area with one or more dies and a frame area outside the die area. Fiducial features within the frame area are identified, and from the fiducial features, an idle frame area is identified. A reference mask design, which corresponds to a reference mask configured to be aligned with the mask, is used to determine a reference density for the idle frame area. The idle frame area of the mask design database is modified to correspond to the reference density. The modified mask design database is then available for further use including manufacturing the mask.
摘要翻译： 公开了一种通过使一组中的掩模之间的框区域中的掩模材料的密度同步来减少层重叠误差的方法。 一种示例性方法包括创建对应于掩模并且包含具有一个或多个管芯的管芯区域和管芯区域外部的框架区域的掩模设计数据库。 识别帧区域内的基准特征，并从基准特征中识别空闲帧区域。 使用对应于被配置为与掩模对准的参考掩模的参考掩模设计来确定空闲帧区域的参考密度。 修改掩模设计数据库的空闲帧区域以对应于参考密度。 然后，修改的掩模设计数据库可用于进一步使用，包括制造掩模。
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公开(公告)号：US20130202992A1
公开(公告)日：2013-08-08
申请号：US13369061
申请日：2012-02-08
申请人： Chia-Jen Chen , Anthony Yen , Hsin-Chang Lee , Sheng-Chi Chin
发明人： Chia-Jen Chen , Anthony Yen , Hsin-Chang Lee , Sheng-Chi Chin
摘要： Provided is a method for reducing phase defects on many different types of semiconductor mask blanks. The method includes receiving a semiconductor mask blank substrate, creating alignment marks on the surface of the substrate, performing an inspection of the surface of the substrate to locate a plurality of surface defects, and repairing the plurality of surface defects on the surface of the substrate. A semiconductor mask is also provided that includes a repaired substrate a multilayer stack comprising a plurality of molybdenum and silicon layers, a capping layer, an absorber layer, and in some instances a photoresist layer.
摘要翻译： 提供了一种用于减少许多不同类型的半导体掩模坯料上的相缺陷的方法。 该方法包括：接收半导体掩模空白基板，在基板的表面上产生对准标记，对基板的表面进行检查以定位多个表面缺陷，以及修复基板表面上的多个表面缺陷 。 还提供了一种半导体掩模，其包括修复的衬底，包括多个钼和硅层的多层叠层，覆盖层，吸收层，并且在一些情况下为光致抗蚀剂层。
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15.发明申请Phase Shift Mask for Extreme Ultraviolet Lithography and Method of Fabricating Same 有权用于极紫外光刻的相移掩模及其制造方法公开(公告)号：US20140038086A1
公开(公告)日：2014-02-06
申请号：US13564198
申请日：2012-08-01
申请人： Chih-Tsung Shih , Pei-Cheng Hsu , Shinn-Sheng Yu , Tsiao-Chen Wu , Yen-Cheng Lu , Shu-Hao Chang , Chia-Jen Chen , Hsin-Chang Lee , Anthony Yen
发明人： Chih-Tsung Shih , Pei-Cheng Hsu , Shinn-Sheng Yu , Tsiao-Chen Wu , Yen-Cheng Lu , Shu-Hao Chang , Chia-Jen Chen , Hsin-Chang Lee , Anthony Yen
摘要： A mask and method of fabricating same are disclosed. In an example, a mask includes a substrate, a reflective multilayer coating disposed over the substrate, an Ag2O absorber layer disposed over the reflective multilayer coating, and a tantalum-containing absorber layer disposed over the Ag2O absorber layer. The tantalum-containing absorber layer is disposed over the Ag2O absorber layer outside a mask image region of the mask, such that the mask image region of the mask is free of the tantalum-containing absorber layer. In an example, the tantalum-containing absorber layer is disposed over the Ag2O absorber layer adjacent to the mask image region.
摘要翻译： 公开了一种掩模及其制造方法。 在一个示例中，掩模包括基板，设置在基板上的反射多层涂层，设置在反射多层涂层上的Ag 2 O吸收层，以及设置在Ag 2 O吸收层上的含钽吸收层。 含钽吸收层设置在掩模的掩模图像区域外侧的Ag 2 O吸收体层上，使得掩模的掩模图像区域不含含钽吸收层。 在一个实例中，含钽吸收层设置在与掩模图像区域相邻的Ag 2 O吸收层上。
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公开(公告)号：US20130337370A1
公开(公告)日：2013-12-19
申请号：US13495291
申请日：2012-06-13
申请人： Hsin-Chang Lee , Pei-Cheng Hsu , Chia-Jen Chen , Anthony Yen
发明人： Hsin-Chang Lee , Pei-Cheng Hsu , Chia-Jen Chen , Anthony Yen
摘要： A photomask having a machine-readable identifying mark and suitable for manufacturing integrated circuit devices and a method for forming the photomask and identifying mark are disclosed. An exemplary embodiment includes receiving a design layout corresponding to a pattern to be formed on a photomask blank. A specification of an identifying code is also received along with the photomask blank, which includes a substrate, a reflective layer, and an absorptive layer. A first patterning is performed using the design layout. A second patterning is performed using the specification of the identifying code.
摘要翻译： 公开了一种具有机读识别标记并适于制造集成电路器件的光掩模和用于形成光掩模和识别标记的方法。 示例性实施例包括接收与在光掩模坯件上形成的图案相对应的设计布局。 识别码的规格也与包括基底，反射层和吸收层的光掩模坯料一起被接收。 使用设计布局进行第一图案化。 使用识别码的说明来执行第二图案化。
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17.发明授权公开(公告)号：US08589828B2
公开(公告)日：2013-11-19
申请号：US13398923
申请日：2012-02-17
申请人： Hsin-Chang Lee , Chia-Jen Chen , Lee-Chih Yeh , Anthony Yen
发明人： Hsin-Chang Lee , Chia-Jen Chen , Lee-Chih Yeh , Anthony Yen
CPC分类号： G03F1/00 , G03F1/20 , G03F1/22 , G03F1/36 , G03F1/42 , G03F1/70 , G06F17/5081 , G06F19/00 , G21K5/00
摘要： A method for reducing layer overlay errors by synchronizing the density of mask material in the frame area across the masks in a set is disclosed. An exemplary method includes creating a mask design database corresponding to a mask and containing a die area with one or more dies and a frame area outside the die area. Fiducial features within the frame area are identified, and from the fiducial features, an idle frame area is identified. A reference mask design, which corresponds to a reference mask configured to be aligned with the mask, is used to determine a reference density for the idle frame area. The idle frame area of the mask design database is modified to correspond to the reference density. The modified mask design database is then available for further use including manufacturing the mask.
摘要翻译： 公开了一种通过使一组中的掩模之间的框区域中的掩模材料的密度同步来减少层重叠误差的方法。 一种示例性方法包括创建对应于掩模并且包含具有一个或多个管芯的管芯区域和管芯区域外部的框架区域的掩模设计数据库。 识别帧区域内的基准特征，并从基准特征中识别空闲帧区域。 使用对应于被配置为与掩模对准的参考掩模的参考掩模设计来确定空闲帧区域的参考密度。 修改掩模设计数据库的空闲帧区域以对应于参考密度。 然后，修改的掩模设计数据库可用于进一步使用，包括制造掩模。
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18.发明授权公开(公告)号：US08656318B2
公开(公告)日：2014-02-18
申请号：US13464116
申请日：2012-05-04
申请人： Hsin-Chang Lee , Chia-Jen Chen , Yeh Lee-Chih , Sheng-Chi Chin , Ting-Hao Hsu , Anthony Yen
发明人： Hsin-Chang Lee , Chia-Jen Chen , Yeh Lee-Chih , Sheng-Chi Chin , Ting-Hao Hsu , Anthony Yen
IPC分类号： G06F17/50
摘要： A method and system for measuring layer overlay and for inspecting a mask for defects unrelated to overlay utilizing a singe comprehensive tool is disclosed. An exemplary method includes receiving a mask design database that corresponds to a mask and has a die area with a mask database feature. A mask image of the mask is received, and a comprehensive inspection system compares the mask image to the mask design database in order to detect mask defects that are not related to layer alignment. The system produces mask defect information corresponding to the mask defects. The comprehensive inspection system also compares the mask image to the mask design database to determine a database-to-mask offset. From the database-to-mask offset, a mask overlay characteristic is determined.
摘要翻译： 公开了一种用于测量层叠覆盖层的方法和系统，并且用于使用单个综合工具来检查与覆盖无关的缺陷的掩模。 一种示例性方法包括接收对应于掩模并且具有掩模数据库特征的管芯区域的掩模设计数据库。 接收掩模的掩模图像，并且综合检查系统将掩模图像与掩模设计数据库进行比较，以便检测与层对齐无关的掩模缺陷。 系统产生对应于掩模缺陷的掩模缺陷信息。 综合检查系统还将掩模图像与掩模设计数据库进行比较，以确定数据库对掩模偏移量。 从数据库到掩码偏移，确定掩模覆盖特性。
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公开(公告)号：US08962222B2
公开(公告)日：2015-02-24
申请号：US13495291
申请日：2012-06-13
申请人： Hsin-Chang Lee , Pei-Cheng Hsu , Chia-Jen Chen , Anthony Yen
发明人： Hsin-Chang Lee , Pei-Cheng Hsu , Chia-Jen Chen , Anthony Yen
摘要： A photomask having a machine-readable identifying mark and suitable for manufacturing integrated circuit devices and a method for forming the photomask and identifying mark are disclosed. An exemplary embodiment includes receiving a design layout corresponding to a pattern to be formed on a photomask blank. A specification of an identifying code is also received along with the photomask blank, which includes a substrate, a reflective layer, and an absorptive layer. A first patterning is performed using the design layout. A second patterning is performed using the specification of the identifying code.
摘要翻译： 公开了一种具有机读识别标记并适于制造集成电路器件的光掩模和用于形成光掩模和识别标记的方法。 示例性实施例包括接收与在光掩模坯件上形成的图案相对应的设计布局。 识别码的规格也与包括基底，反射层和吸收层的光掩模坯料一起被接收。 使用设计布局进行第一图案化。 使用识别码的说明来执行第二图案化。
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20.发明授权公开(公告)号：US07999910B2
公开(公告)日：2011-08-16
申请号：US11115433
申请日：2005-04-27
CPC分类号： G03F7/38
摘要： The present disclosure provides a system and method for manufacturing a mask for semiconductor processing. In one example, the system includes at least one exposure unit configured to select a recipe for a later baking process in a post treatment unit, a buffer unit coupled to the exposure unit and configured to move the mask substrate from the exposure unit to the post treatment unit without exposing the mask substrate to the environment; and the post treatment unit coupled to the buffer unit and the exposure unit and configured to perform a baking process on the mask substrate using baking parameters associated with the recipe selected by the exposure unit.
摘要翻译： 本公开提供了一种用于制造用于半导体处理的掩模的系统和方法。 在一个示例中，系统包括至少一个曝光单元，其被配置为在后处理单元中选择用于稍后烘焙处理的配方，缓冲单元，其耦合到曝光单元并且被配置为将掩模基板从曝光单元移动到柱 处理单元，而不将掩模基板暴露于环境中; 以及所述后处理单元，其耦合到所述缓冲单元和所述曝光单元，并且被配置为使用与由所述曝光单元选择的所述配方相关联的烘焙参数对所述掩模基板进行烘烤处理。
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