公开(公告)号：US20180114343A1

公开(公告)日：2018-04-26

申请号：US15299724

申请日：2016-10-21

Applicant: DISNEY ENTERPRISES, INC.

Inventor： Kenneth J. Mitchell ,  Charalampos Koniaris ,  Jose Antonio Iglesias-Guitian ,  Bochang Moon ,  Eric Smolikowski

IPC: G06T11/00 ,  G06T7/40 ,  G06K9/62

CPC classification number: G06T11/001 ,  G06F9/3885 ,  G06F15/8007 ,  G06K9/00986 ,  G06K9/6215 ,  G06K9/6267 ,  G06T7/408 ,  G06T7/90 ,  G06T2207/10024 ,  G06T2207/20076

Abstract: Views of a virtual space may be presented based on predicted colors of individual pixels of individual frame images that depict the views of the virtual space. Predictive models may be assigned to individual pixels that predict individual pixel colors of individual pixels at individual time points. Individual models may be updated and/or reprojected to other pixels based on comparisons of the predicted pixel colors and colors specified by in a raster input signal.

公开(公告)号：US20180081687A1

公开(公告)日：2018-03-22

申请号：US15272613

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  Lucian Codrescu

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F15/80

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/382 ,  G06F9/3834 ,  G06F9/3855 ,  G06F12/0875 ,  G06F15/8007 ,  G06F2212/452

Abstract: A method of determining an execution order of memory operations performed by a processor includes executing at least one single-instruction, multiple-data (SIMD) scatter operation by the processor to store data to a memory. The method further includes executing one or more instructions by the processor to determine the execution order of a set of memory operations. The set of memory operations includes the at least one SIMD scatter operation.

公开(公告)号：US09910826B2

公开(公告)日：2018-03-06

申请号：US14670684

申请日：2015-03-27

Applicant: International Business Machines Corporation

Inventor： Leopold Grinberg ,  Karen A. Magerlein

IPC: G06F17/16 ,  G06F15/80 ,  G06F9/30

CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30036 ,  G06F15/8007 ,  G06F15/8053

Abstract: Implementing a 1D stencil code via SIMD instructions on a computer with vector registers having N processing elements (PEs), among them a set of coefficient vector registers, a set of at most N data vector registers, and a set of result vector registers. The M stencil coefficients are loaded in a particular pattern into M+N−1 coefficient vector registers. Successive sets of N consecutive data values are received, and each data value of a set is loaded into all PEs of a data vector register of the set of data vector registers. The result vector registers accumulate sums of products of consecutive coefficient vector registers with corresponding data vector registers. The contents of any result vector register containing a sum of all coefficient vector register-data vector register products is output, and the result vector register is reused for accumulating.

公开(公告)号：US09892089B2

公开(公告)日：2018-02-13

申请号：US14146747

申请日：2014-01-03

Applicant: Infineon Technologies AG

Inventor： Tomaz Felicijan

IPC: G06F9/00 ,  G06F15/80 ,  G06F9/38 ,  G06F21/60 ,  G06F21/55 ,  G06F9/30

CPC classification number: G06F15/8007 ,  G06F9/3001 ,  G06F9/3836 ,  G06F21/60 ,  G06F21/755

Abstract: In various embodiments an arithmetic logical unit array is provided, which may include: at least two data registers for storing data, a plurality of fixed instruction registers for storing machine code instructions, and at least one programmable instruction register for storing instruction data being representative for a machine code instruction. A selection circuit of the arithmetic logical unit array may be configured to select one of the machine code instructions from the fixed instruction registers or the machine code instruction represented by the instruction data. An arithmetic logical unit of the arithmetic logical unit array may be configured to apply an operation in accordance with the machine code instruction selected by the selection circuit to the data stored in the data registers.

公开(公告)号：US20170371393A1

公开(公告)日：2017-12-28

申请号：US15189054

申请日：2016-06-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Syed Zohaib M. Gilani ,  Jiasheng Chen ,  QingCheng Wang ,  YunXiao Zou ,  Michael Mantor ,  Bin He ,  Timour T. Paltashev

IPC: G06F1/32 ,  G06F15/80

CPC classification number: G06F15/8007 ,  G06F1/3234 ,  G06F1/3243 ,  G06T15/005 ,  Y02D10/152

Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.

公开(公告)号：US20170235575A1

公开(公告)日：2017-08-17

申请号：US15353549

申请日：2016-11-16

Applicant: Intel Corporation

Inventor： Mohammad Abdallah

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30174 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30098 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/3867 ,  G06F9/3879 ,  G06F9/45516 ,  G06F12/0875 ,  G06F15/8007 ,  G06F2212/452

Abstract: A method for supporting architecture speculation in an out of order processor is disclosed. The method comprises fetching two threads into the processor, wherein a first thread executes in a speculative state and a second thread executes in a non-speculative state. The method also comprises enabling a speculative scope for an execution of the first thread and a non-speculative scope for an execution of the second thread in an architecture of the processor, wherein the speculative scope and the non-speculative scope can both be fetched into the architecture and be present concurrently.

公开(公告)号：US20170177349A1

公开(公告)日：2017-06-22

申请号：US14977356

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Charles R. Yount ,  Antonio C. Valles ,  Indraneil M. Gokhale ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/38

CPC classification number: G06F9/30029 ,  G06F9/30 ,  G06F9/3802 ,  G06F9/3818 ,  G06F15/8007

Abstract: A processor includes an execution unit to execute instructions to load indices from an array of indices, optionally perform a gather, and prefetch (to a specified cache) elements for a future gather from arbitrary locations in memory. The execution unit includes logic to load, for each element to be gathered or prefetched, an index value to be used in computing the address in memory for the element. The index value may be retrieved from an array of indices that is identified for the instruction. The execution unit includes logic to compute the address based on the sum of a base address that is specified for the instruction and the index value that was retrieved for the data element, with or without scaling. The execution unit includes logic to store gathered data elements in contiguous locations in a destination vector register that is specified for the instruction.

公开(公告)号：US20170147529A1

公开(公告)日：2017-05-25

申请号：US15423868

申请日：2017-02-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shorin KYO

IPC: G06F15/80

CPC classification number: G06F15/8007 ,  G06F15/8015

Abstract: Technology to suppress the drop in SIMD processor efficiency that occurs when exchanging two-dimensional data in a plurality of rectangular regions, between an external section and a plurality of processor elements in an SIMD processor, so that one rectangular region corresponds to one processor element. In the SIMD processor, an address storage unit in a memory controller is capable of setting N number of addresses Ai (i=1 through N) in an external memory by utilizing a control processor. A parameter storage unit is capable of setting a first parameter OSV, a second parameter W, and a third parameter L by utilizing a control processor. A data transfer unit executes the transfer of data between an external memory, and the buffers in N number of processor elements contained in the applicable SIMD processor, based on the contents of the address storage unit and the parameter storage unit.

公开(公告)号：US20170147340A1

公开(公告)日：2017-05-25

申请号：US15396568

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F12/0897

CPC classification number: G06F9/3016 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/384 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F15/8007 ,  G06F21/602 ,  G06F2212/452 ,  G06F2212/68 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/125

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US09632979B2

公开(公告)日：2017-04-25

申请号：US14727826

申请日：2015-06-01

Applicant: Intel Corporation

Inventor： Satyajit Sarangi ,  Thomas F. Raoux

IPC: G06F15/80 ,  G06F9/30 ,  G06T1/20

CPC classification number: G06F15/8007 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/3851 ,  G06T1/20 ,  G06T2200/28

Abstract: An apparatus and method are described for performing a prefix sum. For example, one embodiment of an apparatus comprises: a graphics processor unit comprising one or more execution units to execute single instruction multiple data (SIMD) instructions, the GPU to be provided with a plurality of data elements as input for a prefix sum operation; a first register of the GPU to store the plurality of data elements in specified data element positions; and the one or more execution units to perform a series of single instruction multiple data (SIMD) operations using the plurality of data elements, the SIMD operations performed using regioning techniques to generate the prefix sum, the SIMD operations including a first plurality of simultaneous addition operations to add specified data elements to generate intermediate results and further including a second plurality of simultaneous addition operations to add the intermediate results to other intermediate results to generate the prefix sum.