公开(公告)号：US20230238980A1

公开(公告)日：2023-07-27

申请号：US17581516

申请日：2022-01-21

Applicant: Texas Instruments Incorporated

Inventor： Abdullah Yilmaz

IPC: H03M1/20

CPC classification number: H03M1/205

Abstract: A digital-to-analog converter (DAC) for converting a digital input word to an analog output signal includes a string DAC, a first interpolator and a second interpolator. The string DAC outputs a first voltage and a second voltage in response to M most significant bits of the digital input word. The first interpolator interpolates between the first and second voltages in response to middle Q least significant bits of the digital input word and provides a first interpolated voltage. The second interpolator interpolates between the first interpolated voltage and the second voltage in response to lower P least significant bits of the digital input word.

公开(公告)号：US09207705B2

公开(公告)日：2015-12-08

申请号：US13670779

申请日：2012-11-07

Applicant: Apple Inc.

Inventor： Greg M Hess ,  James E Burnette, II

IPC: G01R31/28 ,  G06F1/04 ,  G01R31/3185 ,  G01R31/317 ,  H03M1/20 ,  H03M1/08

CPC classification number: G06F1/04 ,  G01R31/31709 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/31858 ,  G01R31/318594 ,  G11B20/10398 ,  H03M1/0836 ,  H03M1/205 ,  H04L1/205

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

Abstract translation: 公开了可以允许在时钟分配网络中检测周期和相位抖动的抖动检测电路的实施例。 抖动检测电路可以包括相位选择器，数据发生器，延迟链，逻辑电路和时钟存储元件。 相位选择器可以用于选择要用于发射时钟的时钟相位，并且数据发生器可以用于响应于发射时钟产生数据信号。 延迟链可以产生取决于数据信号的多个输出，并且时钟控制的存储元件可以用于从延迟链捕获多个输出，其可以通过逻辑电路与预期数据进行比较。

公开(公告)号：US20140129868A1

公开(公告)日：2014-05-08

申请号：US13670779

申请日：2012-11-07

Applicant: APPLE INC.

Inventor： Greg M Hess ,  James E Burnette, II

IPC: G06F1/08

CPC classification number: G06F1/04 ,  G01R31/31709 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/31858 ,  G01R31/318594 ,  G11B20/10398 ,  H03M1/0836 ,  H03M1/205 ,  H04L1/205

Abstract: Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

Abstract translation: 公开了可以允许在时钟分配网络中检测周期和相位抖动的抖动检测电路的实施例。 抖动检测电路可以包括相位选择器，数据发生器，延迟链，逻辑电路和时钟存储元件。 相位选择器可以用于选择要用于发射时钟的时钟相位，并且数据发生器可以用于响应于发射时钟产生数据信号。 延迟链可以产生取决于数据信号的多个输出，并且时钟控制的存储元件可以用于从延迟链捕获多个输出，其可以通过逻辑电路与预期数据进行比较。

公开(公告)号：US07999717B2

公开(公告)日：2011-08-16

申请号：US12439757

申请日：2007-09-04

Applicant: Takeshi Ohkawa ,  Koichi Ono ,  Kouji Matsuura ,  Yukitosi Yamashita ,  Junji Toyomura ,  Shogo Nakamura ,  Norifumi Kanagawa

Inventor： Takeshi Ohkawa ,  Koichi Ono ,  Kouji Matsuura ,  Yukitosi Yamashita ,  Junji Toyomura ,  Shogo Nakamura ,  Norifumi Kanagawa

IPC: H03M1/36

CPC classification number: H03M1/0863 ,  H03M1/0682 ,  H03M1/141 ,  H03M1/205 ,  H03M1/365

Abstract: A folding circuit and an analog-to-digital converter wherein a response to small signals is improved, a load on a clock signal can be reduced, and the increase of circuit area can be prevented. The circuit includes a reference voltage generating circuit that generates a plurality of differential voltages as reference voltages, and a plurality of amplification circuits that convert differential voltages between the plurality of reference voltages and an analog input voltage to differential currents, and output these differential currents. The output ends of the amplification circuits are alternately connected. Each of the amplification circuit is configured by a differential amplifier circuit having cascode output transistors (145, 146). A switch (144), which is turned on in synchronization with the control clock, is provided between the both sources of the cascode output transistors (145,146).

Abstract translation: 折叠电路和模数转换器，其中对小信号的响应得到改善，可以减少对时钟信号的负担，并且可以防止电路面积的增加。 该电路包括产生多个差分电压作为参考电压的参考电压产生电路和将多个参考电压之间的差分电压与模拟输入电压转换成差分电流的多个放大电路，并输出这些差分电流。 放大电路的输出端交替连接。 每个放大电路由具有共源共栅输出晶体管（145,146）的差分放大器电路构成。 在共源共栅输出晶体管（145,146）的两个源之间提供与控制时钟同步导通的开关（144）。

公开(公告)号：US07940200B2

公开(公告)日：2011-05-10

申请号：US12637211

申请日：2009-12-14

Applicant: Tomohiko Ito ,  Tetsuro Itakura

Inventor： Tomohiko Ito ,  Tetsuro Itakura

IPC: H03M1/10

CPC classification number: H03M1/1023 ,  H03M1/0682 ,  H03M1/205 ,  H03M1/365 ,  H03M1/745

Abstract: There is disclosed a calibration method for an A/D converter. The A/D converter includes a first amplifier to amplify first and second voltage signals, a second amplifier to amplify the first and second voltage signals amplified by the first amplifier, and a comparator to compare the first and second voltage signals amplified by the second amplifier. The calibration method performs short-circuiting input ports of the second amplifier, comparing the first and second voltage signals inputted to the comparator to obtain a first result, calibrating output voltage of the second amplifier according to the first result, short-circuiting input ports of the first amplifier, opening the short-circuited input ports of the second amplifier, comparing the first and second voltage signals inputted to the comparator to obtain a second result, and calibrating output voltage of the first amplifier according to the second result.

Abstract translation: 公开了一种用于A / D转换器的校准方法。 A / D转换器包括：放大第一和第二电压信号的第一放大器;放大由第一放大器放大的第一和第二电压信号的第二放大器;以及比较器，用于比较由第二放大器放大的第一和第二电压信号; 。 校准方法执行第二放大器的短路输入端口，比较输入到比较器的第一和第二电压信号以获得第一结果，根据第一结果校准第二放大器的输出电压，短路输入端口 第一放大器，打开第二放大器的短路输入端口，比较输入到比较器的第一和第二电压信号以获得第二结果，并根据第二结果校准第一放大器的输出电压。

公开(公告)号：US20100315271A1

公开(公告)日：2010-12-16

申请号：US12791963

申请日：2010-06-02

Applicant: Shine CHUNG

Inventor： Shine CHUNG

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/361 ,  H03M1/1038 ,  H03M1/205

Abstract: An integrated circuit that is capable of converting an analog signal to at least one digital signal is provided. The integrated circuit includes a first input end capable of receiving a first analog signal. A first set of 2n-1 inverters are capable of quantizing the first analog signal and outputting a first set of 2n-1 digital values. Each of the first set of 2n-1 digital values is either 0 or 1. A first adder is coupled with the first set of 2n-1 inverters. The first adder is capable of summing the first set of 2n-1 digital values, outputting a first integer value that is capable of corresponding to at least one digital signal.

Abstract translation: 提供了能够将模拟信号转换为至少一个数字信号的集成电路。 集成电路包括能够接收第一模拟信号的第一输入端。 第一组2n-1个反相器能够量化第一模拟信号并输出​​第一组2n-1个数字值。 第一组2n-1数字值中的每一个都是0或1.第一加法器与第一组2n-1个反相器耦合。 第一加法器能够对第一组2n-1数字值求和，输出能够对应于至少一个数字信号的第一整数值。

公开(公告)号：US20100231430A1

公开(公告)日：2010-09-16

申请号：US12717237

申请日：2010-03-04

Applicant: Yuji NAKAJIMA

Inventor： Yuji NAKAJIMA

IPC: H03M1/12 ,  H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/45183 ,  H03F2200/378 ,  H03F2200/78 ,  H03F2203/45138 ,  H03M1/205

Abstract: An amplifier that is operated between first and second power supplies includes a transistor pair having control terminals to which input signals are input, a load resistor pair that is provided between each transistor of the transistor pair and the first power supply, a constant current source that is provided between the second power supply and the transistor pair, and a first switch that is connected with the constant current source in series between the second power supply and the transistor pair, the first switch being turned on or off in accordance with a clock signal.

Abstract translation: 在第一和第二电源之间操作的放大器包括具有输入信号的控制端子的晶体管对，设置在晶体管对的每个晶体管和第一电源之间的负载电阻器对，恒流源， 设置在所述第二电源和所述晶体管对之间，以及第一开关，其与所述恒定电流源串联连接在所述第二电源和所述晶体管对之间，所述第一开关根据时钟信号导通或截止 。

公开(公告)号：US20100014607A1

公开(公告)日：2010-01-21

申请号：US12497910

申请日：2009-07-06

Applicant: Masaya Kibune ,  Hisakatsu Yamaguchi

Inventor： Masaya Kibune ,  Hisakatsu Yamaguchi

IPC: H04L25/49 ,  H03M1/12

CPC classification number: H03M1/205 ,  H03M1/108 ,  H03M1/109 ,  H03M1/365

Abstract: An AD converter includes a first amplitude circuit, a second amplitude circuit, and a determination circuit. A control signal line controls a first amplitude gain of the first amplitude circuit and a second amplitude gain of the second amplitude circuit.

Abstract translation: AD转换器包括第一幅度电路，第二幅度电路和确定电路。 控制信号线控制第一幅度电路的第一幅度增益和第二幅度电路的第二幅度增益。

公开(公告)号：US5805096A

公开(公告)日：1998-09-08

申请号：US764834

申请日：1996-12-12

Applicant: Richard Morisson ,  Pieter Vorenkamp

Inventor： Richard Morisson ,  Pieter Vorenkamp

IPC: H03M1/20 ,  H03M1/36 ,  H03M1/14

CPC classification number: H03M1/205 ,  H03M1/365

Abstract: An A/D converter in which an interpolation circuit (15, 16, 17, 18) makes weighted combinations of reference crossing signals (A/Ac,B/Bc) provided by an input circuit (100, 200), so as to obtain an expanded set of reference crossing signals (A/Ac+A1/Ac1 . . . A7/Ac7, B/Bc+B1/Bc1 . . . Bc7). The interpolation circuit (15, 16, 17, 18) is arranged to make at least one weighted combination of reference crossing signals with weighting factors which have a non-integer ratio so as to compensate for a non-linearity in the reference crossing signals (A/Ac,B/Bc). Accordingly, a better compromise is obtained between accuracy, on the one hand, and circuit complexity, on the other hand.

Abstract translation: 一种A / D转换器，其中内插电路（15,16,17,18）进行由输入电路（100,200）提供的参考交叉信号（A / Ac，B / Bc）的加权组合，以便获得 一组扩展的参考交叉信号（A / Ac + A1 / Ac1 ... A7 / Ac7，B / Bc + B1 / Bc1 ... Bc7）。 插值电路（15,16,17,18）被布置成使参考交叉信号与具有非整数比的加权因子的至少一个加权组合以补偿参考交叉信号中的非线性（ A / Ac，B / Bc）。 因此，另一方面，一方面在精度与电路复杂性之间获得更好的妥协。

公开(公告)号：US5291198A

公开(公告)日：1994-03-01

申请号：US887761

申请日：1992-05-29

Applicant: Andrew G. F. Dingwall ,  Fu-Lung Hsueh

Inventor： Andrew G. F. Dingwall ,  Fu-Lung Hsueh

IPC: H03M1/20 ,  H03M1/36

CPC classification number: H03M1/204 ,  H03M1/205 ,  H03M1/365

Abstract: A flash-type analog-to-digital converter (ADC) uses only 2.sup.n-m comparators coupled to the analog input line to generate a n-bit digital output signal. Each pair of these actual comparators are coupled, in parallel, to 2.sup.m pseudocomparators which provide values representing comparisons of the input signal value to respective reference values between the reference values used by the actual comparators. The output signals of each pair of actual comparators are combined in respectively different proportions at each of the pseudocomparators. In this manner, the output signals of the actual comparators are averaged to produce the interstitial comparison values. In one embodiment of the invention, the ADC is implemented in BiCMOS technology with a bipolar differential input stage and a CMOS latching comparator. Signals are distributed from the actual comparators to the pseudocomparators via a pair of resistive ladder networks. In other embodiments of the invention the ADC is implemented in CMOS technology and the pseudocomparators use ratioed transistor widths and ratioed capacitors to proportionally divide the output signals of the actual comparators in order to generate the interstitial output values. A final embodiment of the invention combines two averaging flash ADCs to form a novel subranging ADC.

Abstract translation: 闪存型模数转换器（ADC）仅使用耦合到模拟输入线的2n-m个比较器来产生n位数字输出信号。 这些实际比较器中的每一对并联耦合到2m伪同步器，其提供表示将输入信号值与实际比较器使用的参考值之间的相应参考值进行比较的值。 每对实际比较器的输出信号在每个伪同步器上以不同的比例组合。 以这种方式，实际比较器的输出信号被平均以产生间隙比较值。 在本发明的一个实施例中，ADC采用BiCMOS技术实现，具有双极性差分输入级和CMOS锁存比较器。 信号通过一对电阻梯形网络从实际的比较器分布到伪同步器。 在本发明的其他实施例中，ADC以CMOS技术实现，并且伪同步器使用比例的晶体管宽度和比例的电容器来成比例地划分实际比较器的输出信号，以便产生间隙输出值。 本发明的最终实施例组合了两个平均闪光ADC，以形成新型的Subranging ADC。