公开(公告)号：US07120851B2

公开(公告)日：2006-10-10

申请号：US10649785

申请日：2003-08-28

申请人： Yu Jing Ting ,  Noriyoshi Ito ,  Hiroshi Katsuragawa

发明人： Yu Jing Ting ,  Noriyoshi Ito ,  Hiroshi Katsuragawa

IPC分类号： H03M13/00 ,  H03M13/03

CPC分类号： H03M13/3927 ,  H03M13/2978

摘要： The present invention relates generally to error-correction coding and, more particularly, to a decoder for concatenated codes, e.g., turbo codes. The present invention provides a decoder for decoding encoded data, the decoder comprising: a processor having an input which receives probability estimates for a block of symbols, and which is arranged to calculates probability estimates for said symbols in a next iterative state; normalising means which normalises said next states estimates; a switch that receives both said normalised and said unnormalised next state estimates, the output of the switch being coupled to the input of the processor; wherein the switch is arranged to switch between the normalised and unnormalised next state estimates depending on the iterative state.

摘要翻译： 本发明一般涉及纠错编码，更具体地说，涉及用于级联码（例如，turbo码）的解码器。 本发明提供了一种用于对编码数据进行解码的解码器，该解码器包括：一个处理器，具有一个输入，该输入接收一个符号块的概率估计，并且被配置为在下一个迭代状态下计算所述符号的概率估计; 规范化所述下一状态估计的正规化装置; 接收所述归一化和所述非标准化下一状态估计的开关，所述开关的输出耦合到所述处理器的输入; 其中所述开关被布置为根据迭代状态在归一化和非标准化的下一状态估计之间切换。

公开(公告)号：US07012975B2

公开(公告)日：2006-03-14

申请号：US09952309

申请日：2001-09-12

申请人： Hau Thien Tran ,  Kelly B. Cameron ,  Ba-Zhong Shen ,  Christopher R. Jones

发明人： Hau Thien Tran ,  Kelly B. Cameron ,  Ba-Zhong Shen ,  Christopher R. Jones

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Method and apparatus for performing calculations for forward (alpha) and reverse (beta) metrics in a map decoder. The method includes using a min star (min*) operation to receive the metrics and a priori values as well as forming min star structures from individual min star operations. Two separate outputs from the min star operation may be maintained separately throughout all calculations and combined only when a final value is required. In addition input to the min star operators that are available prior to a particular decoder iteration may be combined separately to allow an increase in speed within decoding iterations. The same principals apply to the more popular max star operation.

公开(公告)号：US07007220B2

公开(公告)日：2006-02-28

申请号：US10087202

申请日：2002-03-01

申请人： Wei-Min Zhang ,  Timothy A. Misko

发明人： Wei-Min Zhang ,  Timothy A. Misko

IPC分类号： H03M13/00

CPC分类号： H03M13/29 ,  H03M13/2978 ,  H04L1/0009 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0076 ,  H04L25/14

摘要： Error correction coding across multiple channels is provided in multi-channel transmission systems. Specifically, redundancy is provided by selecting a portion of original data from each of a plurality of original channels, performing at least one encoding operation using the portions of original data to produce at least one portion of redundancy data, including the portion of redundancy data in at least one redundancy channel, and transmitting the redundancy channel along with the original channels. Error correction is achieved by receiving at least one redundancy channel and a plurality of original channels, selecting a portion of redundancy data from the redundancy channel, selecting a portion of original data from each of the original channels, and performing at least one decoding operation using the portion of redundancy data and the portions of original data to correct at least one error in the portions of original data.

公开(公告)号：US20050022090A1

公开(公告)日：2005-01-27

申请号：US10897201

申请日：2004-07-22

申请人： Kelly Cameron ,  Hau Tran ,  Ba-Zhong Shen ,  Christopher Jones

发明人： Kelly Cameron ,  Hau Tran ,  Ba-Zhong Shen ,  Christopher Jones

IPC分类号： H03M13/15 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H03M13/41 ,  H03M13/45 ,  H04L1/00 ,  G06F7/00 ,  G06F17/30 ,  H03M13/00 ,  H04L5/12 ,  H04L23/02

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

公开(公告)号：US20020061078A1

公开(公告)日：2002-05-23

申请号：US09952312

申请日：2001-09-12

发明人： Kelly B. Cameron

IPC分类号： H04L027/06

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： Method and apparatus for Soft In Soft Out Turbo Code Decoder. Metrics are received by a decoder having SISO unit(s). The SISO unit computes all the alpha values corresponding to a block of data. Of the alpha values computed some alpha values, for example alpha values selected at regular intervals, corresponding to checkpoint values are pushed on a checkpoint stack. Alpha values are computed with some being saved as checkpoint values and some being discarded are computed until the computation reaches a predetermined distance from the end of the block of data. Once the predetermined distance is reached all alpha values are pushed on a computation stack. Once all the values corresponding to the values between the predetermined end of the block and the end of the block have been computed and placed in the computation stack they may be combined with beta values to produce extrinsic values. Once all the values have been used from the computation stack the next checkpoint value can be used to compute another computation stack of alpha values. The alpha values can then be combined with beta values to form extrinsic values and the process continued.

摘要翻译： 软输出Turbo码解码器的方法和装置。 度量由具有SISO单元的解码器接收。 SISO单元计算对应于数据块的所有α值。 计算一些alpha值的Alpha值，例如以定期间隔选择的对应于检查点值的alpha值被推送到检查点堆栈。 计算Alpha值，其中一些被保存为检查点值，并且计算一些被丢弃的值，直到计算达到距数据块结束的预定距离。 一旦达到预定距离，所有的阿尔法值被推送到计算堆栈上。 一旦对应于块的预定端和块结束之间的值的所有值已经被计算并被放置在计算堆栈中，它们可以与β值组合以产生外在值。 一旦从计算堆栈中使用了所有的值，可以使用下一个检查点值来计算alpha值的另一个计算堆栈。 然后可以将α值与β值组合以形成外在值，并且该过程继续。

公开(公告)号：US09250996B2

公开(公告)日：2016-02-02

申请号：US13877650

申请日：2011-10-04

申请人： Tomoyoshi Kobori ,  Steffen Kunze ,  Emil Matus ,  Gerhard Fettweis

发明人： Tomoyoshi Kobori ,  Steffen Kunze ,  Emil Matus ,  Gerhard Fettweis

IPC分类号： G06F11/10 ,  H03M13/11 ,  H03M13/00 ,  H03M13/29 ,  H03M13/27 ,  G06F5/01

CPC分类号： G06F11/1044 ,  G06F5/015 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/1145 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/2775 ,  H03M13/296 ,  H03M13/2978 ,  H03M13/6508 ,  H03M13/6513 ,  H03M13/6566 ,  H03M13/6569 ,  H03M13/6577

摘要： In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.

摘要翻译： 在能够同时处理多个纠错方法和多个码长的多核型纠错处理系统中，互连部分11具有延伸跨越多个纠错处理部分12a-12c的桶形移位器。 可以通过集体地使用多个纠错处理部分12a-12c的组或者通过单独地使用每个单独的纠错处理部分12a-12c来响应于互连配置信息来选择性地执行纠错处理。 利用这种结构，如果计算资源不足，则多个纠错处理部分12a-12c被共同使用，并且如果计算资源过多，则将空闲纠错处理部分分配给另一纠错处理部分。

公开(公告)号：US08930792B2

公开(公告)日：2015-01-06

申请号：US13766891

申请日：2013-02-14

申请人： LSI Corporation

发明人： Shu Li ,  Shaohua Yang ,  Zongwang Li ,  Yang Han

IPC分类号： H03M13/00 ,  H03M13/13 ,  H03M13/29 ,  G11B20/18 ,  H04L1/00

CPC分类号： H03M13/13 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1117 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/2978 ,  H03M13/6325 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

摘要： Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. In some cases the systems include a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit. The common circuit is operable to: shift a combination of both a first sub-message from the first data decoder engine and the second sub-message from the second data decoder engine to yield an shifted output, and disaggregate the shifted output to yield a third sub-message to the first data decoder engine and a fourth sub-message to the second decoder engine.

摘要翻译： 一般涉及数据处理的系统和方法，更具体地涉及用于利用多个数据流进行数据从存储设备的数据恢复的系统和方法。 在一些情况下，系统包括低密度奇偶校验数据解码器电路，其包括至少第一数据解码器引擎和第二数据解码器引擎，每个电耦合到公共电路。 公共电路可操作用于：将来自第一数据解码器引擎的第一子消息和来自第二数据解码器引擎的第二子消息的组合移位以产生移位的输出，并且分解转移的输出以产生第三 子消息发送到第一数据解码器引擎，第四子消息发送到第二解码器引擎。

公开(公告)号：US08811452B2

公开(公告)日：2014-08-19

申请号：US12814157

申请日：2010-06-11

申请人： Eran Pisek ,  Yan Wang

发明人： Eran Pisek ,  Yan Wang

IPC分类号： H04B1/00

CPC分类号： H04L5/0007 ,  H03M13/2739 ,  H03M13/2978 ,  H03M13/2987 ,  H03M13/3972 ,  H03M13/6519 ,  H03M13/6525 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066 ,  H04L25/03171

摘要： A receiver capable of decoding encoded transmissions. The receiver includes a number of receive antennas configured to receive data; a plurality of memory units that store the received data; and a plurality of decoders configured to perform a Turbo decoding operation. Each of the plurality of decoders decodes at least a portion of the received data using at least a portion of a decoding matrix. The receiver also includes a data switch coupled between the plurality of decoders and the plurality of memory units. The data switch configured to vary a decode operation from an long term evolution (LTE) based operation to a Wideband Code Division Multiple Access (WCDMA) operation.

摘要翻译： 一种能够解码编码的传输的接收机。 接收机包括被配置为接收数据的多个接收天线; 存储所接收的数据的多个存储单元; 以及多个解码器，被配置为执行Turbo解码操作。 多个解码器中的每一个使用解码矩阵的至少一部分来解码所接收的数据的至少一部分。 接收机还包括耦合在多个解码器和多个存储器单元之间的数据开关。 数据交换器被配置为将解码操作从基于长期演进（LTE）的操作改变为宽带码分多址（WCDMA）操作。

公开(公告)号：US20140229806A1

公开(公告)日：2014-08-14

申请号：US13766891

申请日：2013-02-14

申请人： LSI CORPORATION

发明人： Shu Li ,  Shaohua Yang ,  Zongwang Li ,  Yang Han

IPC分类号： H03M13/13 ,  G11B20/18

CPC分类号： H03M13/13 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1117 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/2978 ,  H03M13/6325 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

摘要： The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.

摘要翻译： 本发明涉及用于数据处理的系统和方法，更具体地涉及用于执行数据解码的系统和方法。

公开(公告)号：US08719670B1

公开(公告)日：2014-05-06

申请号：US12313512

申请日：2008-11-19

申请人： Marcus Marrow

发明人： Marcus Marrow

IPC分类号： H03M13/00 ,  G11C29/00 ,  G06F11/10 ,  H03M13/29 ,  H03M13/35

CPC分类号： G06F11/1072 ,  G06F11/1008 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1515 ,  H03M13/251 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/2927 ,  H03M13/2978 ,  H03M13/356

摘要： A system for decoding data is disclosed. The system includes: an input interface configured to receive data associated with encoded data; a first decoder configured to decode a first subset of the encoded data to obtain a first portion of decoded data; a second decoder configured to decode a second subset of the encoded data to obtain a second portion of the decoded data, wherein the second portion includes decoded data not included in the first portion; and an output interface configured to output the decoded data.

摘要翻译： 公开了一种用于解码数据的系统。 该系统包括：被配置为接收与编码数据相关联的数据的输入接口; 第一解码器，被配置为对编码数据的第一子集进行解码以获得解码数据的第一部分; 第二解码器，被配置为对编码数据的第二子集进行解码以获得解码数据的第二部分，其中第二部分包括未包括在第一部分中的解码数据; 以及输出接口，被配置为输出解码数据。