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公开(公告)号：US20230113054A1
公开(公告)日：2023-04-13
申请号：US18080524
申请日：2022-12-13
申请人： KIOXIA CORPORATION
发明人： Hiroshi MAEJIMA
摘要： A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
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公开(公告)号：US11625182B2
公开(公告)日：2023-04-11
申请号：US17193904
申请日：2021-03-05
申请人： SK hynix Inc.
发明人： Wan Seob Lee
摘要： The storage device includes a memory controller and a plurality of banks, each of the plurality of banks including a plurality of memory devices. Each of the plurality of memory devices includes: a data selector for selecting and outputting data of a memory device that is included in any one of the plurality of banks based on a bank select signal; a latch unit for storing the data that is output from the data selector; and a transmission control signal generator for generating the bank select signal such that the data that is stored in the latch unit is sequentially output.
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公开(公告)号：US20230100916A1
公开(公告)日：2023-03-30
申请号：US18075027
申请日：2022-12-05
摘要： Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios.
The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.-
公开(公告)号：US20230098708A1
公开(公告)日：2023-03-30
申请号：US17490097
申请日：2021-09-30
发明人： Meng-Sheng Chang , Chia-En Huang , Yih Wang
IPC分类号： G11C16/10 , H01L29/06 , H01L29/423 , G11C16/26 , H01L29/78
摘要： A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.
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公开(公告)号：US20230097416A1
公开(公告)日：2023-03-30
申请号：US17488128
申请日：2021-09-28
发明人： Hang-Ting LUE , Wei-Chen CHEN
IPC分类号： H01L27/11582 , H01L27/11556 , G11C16/10 , G11C16/16 , G11C16/26
摘要： Disclosed is 3D flash memory comprises a gate stack structure, an annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base, and comprising a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrating through the gate stack structure. The first source/drain pillar and the second source/drain pillar, disposed on the dielectric base, located within the annular channel pillar and penetrating through the gate stack structure, wherein the first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the annular channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the annular channel pillar. The first source/drain pillar and the second source/drain pillar are P-type doped.
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公开(公告)号：US11615846B2
公开(公告)日：2023-03-28
申请号：US17832117
申请日：2022-06-03
发明人： Huanyou Zhan , Massimo Rossini , Jun Xu
摘要： Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.
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公开(公告)号：US11615845B2
公开(公告)日：2023-03-28
申请号：US17249284
申请日：2021-02-25
发明人： Toru Ishikawa , Minari Arai
摘要： Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.
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公开(公告)号：US11615839B2
公开(公告)日：2023-03-28
申请号：US17368727
申请日：2021-07-06
发明人： Xiang Yang
IPC分类号： G11C16/04 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/26 , H01L27/11565 , H01L25/065 , H01L27/11582
摘要： In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell while data is stored on a top edge word line that is closest to the etching with variable bits per memory cell. In one example embodiment that implements vertical NAND strings, memory cells connected to the top edge word line and that are on NAND strings adjacent the etching store data as n bits per memory cell and memory cells connected to the top edge word line and that are on NAND strings not adjacent the etching store data as m bits per memory cell, where m>x>n.
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公开(公告)号：US11615833B2
公开(公告)日：2023-03-28
申请号：US17223458
申请日：2021-04-06
发明人： Kwangseob Shin , Jindo Byun , Younghoon Son , Youngdon Choi , Junghwan Choi
IPC分类号： G11C16/26 , G11C11/4091 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4099
摘要： A multi-level signal receiver includes a data sampler circuit and a reference voltage generator circuit. The data sampler includes (M−1) sense amplifiers which compare a multi-level signal having one of M voltage levels different from each other with (M−1) reference voltages. The data sampler generates a target data signal including N bits, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M−1) reference voltages, At least two sense amplifiers of the (M−1) sense amplifiers have different sensing characteristics.
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20.发明申请公开(公告)号：US20230093270A1
公开(公告)日：2023-03-23
申请号：US17654292
申请日：2022-03-10
申请人： Kioxia Corporation
发明人： Xu LI
摘要： A semiconductor storage device of an embodiment includes a plurality of blocks, a voltage supply circuit configured to generate read voltage Vr to be supplied to signal lines, a block decoder capable of setting, for each of the selected blocks, whether the read voltage Vr is applied to word lines, and a sequencer configured to perform operation that reads data. The voltage supply circuit generates power voltage VRD and power voltage VBB that is negative voltage and supplies these voltages to the block decoder. During the reading operation, a value of the power voltage VRD is changed between voltage Vhr and voltage Vlr and a value of the power voltage VBB is changed between voltage Vhb and voltage Vlb. The voltage Vhr is larger than zero volt, and the voltage Vlb is lower than zero volt.
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