公开(公告)号：US20230386893A1

公开(公告)日：2023-11-30

申请号：US17843089

申请日：2022-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Tsai HUNG ,  Yi LIU ,  Guo-Hai ZHANG ,  Ching-Hwa TEY

IPC: H01L21/762 ,  H01L27/12 ,  H01L23/00

CPC classification number: H01L21/76251 ,  H01L27/1203 ,  H01L23/562 ,  H01L23/564

Abstract: A semiconductor structure is provided. The semiconductor structure includes a wafer structure. The wafer structure has a normal region and a trimmed region adjacent to the normal region. A top surface of the trimmed region is lower than a top surface of the normal region. The semiconductor structure includes a dielectric layer and a conductive layer disposed on the wafer structure in the normal region and the trimmed region. The semiconductor structure includes a protective layer disposed on a portion of the dielectric layer in the trimmed region and a portion of the conductive layer in the trimmed region. The semiconductor structure includes another dielectric layer disposed on a portion of the dielectric layer in the normal region and a portion of the conductive layer in the normal region and on the protective layer.

公开(公告)号：US20230384689A1

公开(公告)日：2023-11-30

申请号：US17880700

申请日：2022-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Yen LIU ,  Hui-Fang KUO ,  Chian-Ting HUANG ,  Wei-Cyuan LO ,  Yung-Feng CHENG ,  Chung-Yi CHIU

IPC: G03F7/20

CPC classification number: G03F7/70441

Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

公开(公告)号：US11832446B2

公开(公告)日：2023-11-28

申请号：US17065508

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hock Chun Chin

IPC: H01L29/10 ,  H01L27/11 ,  H10B43/27 ,  H10B43/30 ,  H10B51/20 ,  H01L21/28 ,  H01L29/78 ,  H01L29/792 ,  H10B43/50 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/40111 ,  H10B43/30 ,  H10B51/20 ,  H01L29/40117 ,  H01L29/78391 ,  H01L29/7926 ,  H10B43/35 ,  H10B43/50

Abstract: A three-dimensional (3D) memory device includes a channel structure extending along a first direction and a control gate structure extending along a second direction around the channel structure. Preferably, channel structure includes a negative capacitance (NC) insulating layer, a charge trap structure, and a channel layer, in which the NC insulating layer includes HfZrOx and the charge trap structure includes a blocking layer, a charge trap layer, and a tunneling layer.

公开(公告)号：US20230378275A1

公开(公告)日：2023-11-23

申请号：US17844746

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/66462 ,  H01L29/205 ,  H01L29/7786

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, and a silicon-rich tensile stress layer. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer, and the silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A silicon-rich tensile stress layer is formed on the III-V compound barrier layer. An annealing process is performed after the silicon-rich tensile stress layer is formed. A part of silicon in the silicon-rich tensile stress layer diffuses into the III-V compound barrier layer for forming a silicon-doped III-V compound barrier layer by the annealing process.

公开(公告)号：US20230378167A1

公开(公告)日：2023-11-23

申请号：US17844742

申请日：2022-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823431

Abstract: The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.

公开(公告)号：US11825657B2

公开(公告)日：2023-11-21

申请号：US17700522

申请日：2022-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wen Wang

IPC: H01L29/66 ,  H10B43/30 ,  H01L29/792

CPC classification number: H10B43/30 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device includes a substrate having thereon at least one active area and at least one trench isolation region adjacent to the at least one active area. A charge trapping structure is disposed on the at least one active area and at least one trench isolation region. At least one divot is disposed in the at least one trench isolation region adjacent to the charge trapping structure. A silicon oxide layer is disposed in the at least one divot. A gate oxide layer is disposed on the at least one active area around the charge trapping structure.

公开(公告)号：US11825648B2

公开(公告)日：2023-11-21

申请号：US17323863

申请日：2021-05-18

Applicant: United Microelectronics Corp.

Inventor： Kuo-Hsing Lee ,  Chi-Horn Pai ,  Chang Chien Wong ,  Sheng-Yuan Hsueh ,  Ching Hsiang Tseng ,  Shih-Chieh Hsu

IPC: H10B20/20

CPC classification number: H10B20/20

Abstract: A one-time programmable memory structure including a substrate, a transistor, a capacitor, and an interconnect structure is provided. The transistor is located on the substrate. The capacitor includes a first electrode, a second electrode, and an insulating layer. The first electrode is disposed above the substrate. The second electrode is disposed on the first electrode. The first electrode is located between the second electrode and the substrate. The insulating layer is disposed between the first electrode and the second electrode. The interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode.

公开(公告)号：US20230369448A1

公开(公告)日：2023-11-16

申请号：US18221396

申请日：2023-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Rong Chen ,  Che-Hung Huang ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Chih-Tung Yeh ,  Shin-Chuan Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/7783 ,  H01L29/2003

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.

公开(公告)号：US20230363286A1

公开(公告)日：2023-11-09

申请号：US18224066

申请日：2023-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H10N50/80 ,  G11C11/16 ,  H10N50/01 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

公开(公告)号：US20230363278A1

公开(公告)日：2023-11-09

申请号：US18224711

申请日：2023-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Biao ZHOU

IPC: H10N30/05 ,  H10N30/072 ,  H10N30/80

CPC classification number: H10N30/05 ,  H10N30/072 ,  H10N30/80

Abstract: A method for manufacturing a semiconductor module is provided. The method includes: providing a substrate, wherein the substrate comprises a front side and at least one semiconductor element formed on the front side; forming a shielding structure on the at least one semiconductor element; forming a piezoelectric layer on the shielding structure.