公开(公告)号：US10204784B1

公开(公告)日：2019-02-12

申请号：US15797633

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jinsheng Gao ,  Hui Zang ,  Haigou Huang

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092

Abstract: One illustrative method disclosed herein includes, among other things, forming an initial patterned etch mask above a feature-formation etch mask, the initial patterned etch mask including a plurality of laterally spaced-apart features having a non-uniform spacing, and performing at least one first etching process to remove an entire axial length of at least one of the plurality of features so as to thereby form a modified final patterned etch mask comprised of a plurality of features with a uniform spacing that defines a feature-formation pattern. In this example, the method also includes performing at least one second etching process so as to form a patterned feature-formation etch mask comprising the feature-formation pattern and performing at least one third etching process so as to form a plurality of features in a first layer, the features being formed with the feature-formation pattern.

公开(公告)号：US20190019798A1

公开(公告)日：2019-01-17

申请号：US16133176

申请日：2018-09-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiaoqiang Zhang ,  Hui Zang ,  Ratheesh R. Thankalekshmi ,  Randy W. Mann

IPC: H01L27/11 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  H01L29/66545 ,  H01L29/66818

Abstract: Various aspects include a static random access memory (SRAM) bitcell array structure. In some cases, the SRAM bitcell array structure includes at least one fin in an array of fins in a substrate, where a width of a first portion of the at least one fin is less than a width of a second portion of the at least one fin in the array of fins.

公开(公告)号：US10177151B1

公开(公告)日：2019-01-08

申请号：US15632702

申请日：2017-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanzhen Wang ,  Hui Zang ,  Bingwu Liu

IPC: H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66

Abstract: A method and structure for a semiconductor device that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions, which are within a semiconductor fin and define the active device region(s) for the FINFET(s). Asymmetric trenches are formed in a substrate through asymmetric cuts in sacrificial fins formed on the substrate. The asymmetric cuts have relatively larger gaps between fin portions that are closest to the substrate, and deeper portions of the asymmetric trenches are relatively wider than shallower portions. Channel regions are formed in the substrate below two adjacent fins. Source/drain regions of complementary transistors are formed in the substrate on opposite sides of the channel regions. The asymmetric trenches are filled with an insulator to form a single-diffusion break between two source/drain regions of different ones of the complementary transistors. Also disclosed is a semiconductor structure formed according to the method.

公开(公告)号：US20190006280A1

公开(公告)日：2019-01-03

申请号：US16122259

申请日：2018-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L23/66 ,  H01L29/06

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; an upper conductor extending above, without contacting, the source/drain contact, wherein the upper conductor extends within the dielectric layer to contact the gate conductor within the gate stack.

公开(公告)号：US10170353B2

公开(公告)日：2019-01-01

申请号：US15634091

申请日：2017-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/74 ,  H01L23/48 ,  H01L29/06 ,  H01L29/10 ,  H01L21/762 ,  H01L21/768

Abstract: Devices and methods of fabricating integrated circuit devices for dynamically applying bias to back plates and/or p-well regions are provided. One method includes, for instance: obtaining a wafer with a silicon substrate, at least one first oxide layer, at least one silicon layer, and at least one second oxide layer; forming at least one recess in the wafer; depositing at least one third oxide layer over the wafer and filling the at least one recess; depositing a silicon nitride layer over the wafer; and forming at least one opening having sidewalls and a bottom surface within the filled at least one recess. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20180331232A1

公开(公告)日：2018-11-15

申请号：US15590409

申请日：2017-05-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42356 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A fin is formed that includes a first nanosheet channel layer and a second nanosheet channel layer arranged in a vertical stack. A cavity is formed between a portion of the first nanosheet channel layer and a portion of the second nanosheet channel layer. An epitaxially-grown source/drain region is connected with the portion of the first nanosheet channel layer and the portion of the second nanosheet channel layer. A gate structure is formed that includes a section located in a space between the first nanosheet channel layer and the second nanosheet channel layer. The cavity is surrounded by the first nanosheet channel layer, the second nanosheet channel layer, the section of the gate structure, and the source/drain region to define an air gap spacer.

公开(公告)号：US10121878B1

公开(公告)日：2018-11-06

申请号：US15711415

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Jagar Singh ,  Hui Zang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L21/441 ,  H01L29/06 ,  H01L21/266

Abstract: Field-effect transistor structures for a laterally-diffused metal-oxide-semiconductor (LDMOS) device and methods of forming a LDMOS device. First and second fins are formed on a substrate. A first well of a first conductivity type is arranged partially in the substrate and partially in the first fin. A second well of a second conductivity type is arranged partially in the substrate, partially in the first fin, and partially in the second fin. First and second source/drain regions of the second conductivity type are respectively formed within the first well in the first fin and within the second well in the second fin. Spaced-apart gate structures are formed that overlap with respective portions of the first fin. A doped region of the first conductivity type is arranged within the second well in the first fin between the first and second gate structures.

公开(公告)号：US10103238B1

公开(公告)日：2018-10-16

申请号：US15652890

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Tek Po Rinus Lee ,  Haigou Huang ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L21/311 ,  H01L29/786 ,  H01L21/02

Abstract: Methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a plurality of nanosheet channel layers and a plurality of first sacrificial layers that are alternatingly arranged with the nanosheet channel layers. The body feature is located on a second sacrificial layer. The first sacrificial layers are recessed relative to the nanosheet channel layers to form a plurality of first cavities indented into a sidewall of the body feature. A plurality of dielectric spacers are formed that fill the first cavities. After forming the dielectric spacers, the second sacrificial layer is removed with an etching process to define a second cavity that extends completely beneath the body feature. A dielectric layer is formed in the second cavity.

公开(公告)号：US20180286965A1

公开(公告)日：2018-10-04

申请号：US15475272

申请日：2017-03-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haigou Huang

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/321 ,  H01L29/49 ,  H01L21/3105

Abstract: The disclosure is directed to methods of forming an integrated circuit structure. One method may include: forming a metal gate within a dielectric layer over a substrate; forming an opening within the metal gate; recessing the metal gate such that a height of the metal gate is reduced; forming an insulator over the recessed metal gate and filling the opening; and planarizing the insulator to a top surface of the dielectric layer.

公开(公告)号：US10068902B1

公开(公告)日：2018-09-04

申请号：US15715220

申请日：2017-09-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanping Shen ,  Hui Zang ,  Hsien-Ching Lo ,  Yongjun Shi ,  Randy W. Mann ,  Yi Qi ,  Guowei Xu ,  Wei Hong ,  Jerome Ciavatti ,  Jae Gon Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/06 ,  H01L29/66

Abstract: Disclosed is a method of forming an integrated circuit (IC) structure with multiple non-planar transistors having different effective channel widths. In the method, sacrificial gates are removed from partially completed transistors, creating gate openings that expose sections of semiconductor fins between source/drain regions. Prior to forming replacement metal gates in the gate openings, additional process steps are performed so that, in the resulting IC structure, some transistors have different channel region heights and, thereby different effective channel widths, than others. These steps can include forming isolation regions in the bottoms of some gate openings. Additionally or alternatively, these steps can include filling some gate openings with a sacrificial material, recessing the sacrificial material to expose fin tops within those gate openings, either recessing the fin tops or forming isolation regions in the fin tops, and removing the sacrificial material. Also disclosed is an IC structure formed according to the method.