公开(公告)号：US20180233370A1

公开(公告)日：2018-08-16

申请号：US15951149

申请日：2018-04-11

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/161 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

公开(公告)号：US20180233369A1

公开(公告)日：2018-08-16

申请号：US15950773

申请日：2018-04-11

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Pouya Hashemi ,  Hemanth Jagannathan ,  Choonghyun Lee ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L29/161 ,  H01L29/78

Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.

公开(公告)号：US12183826B2

公开(公告)日：2024-12-31

申请号：US17302986

申请日：2021-05-18

Applicant: International Business Machines Corporation

Inventor： Choonghyun Lee ,  Soon-Cheon Seo ,  Injo Ok ,  Alexander Reznicek

IPC: H01L29/786 ,  H01L21/324 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

Abstract: A semiconductor structure, and a method of making the same includes a fin extending upward from a substrate, an epitaxially grown bottom source/drain region in direct contact with the substrate and a bottom portion of the fin. A bottom surface and sidewalls of a metal silicide layer are in direct contact with the epitaxially grown bottom source/drain region. A bottom spacer is located above and in direct contact with the metal silicide layer and a portion of the epitaxially grown bottom source/drain region not covered by the metal silicide layer, the bottom spacer surrounding the fin.

公开(公告)号：US12136671B2

公开(公告)日：2024-11-05

申请号：US17566875

申请日：2021-12-31

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Choonghyun Lee ,  Takashi Ando ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Channel engineering is employed to obtain a gate-all-around field-effect transistor having an asymmetric threshold voltage. A dual channel profile enables a steep potential distribution near the source side that enhances the lateral channel electric field and thus increases the carrier mobility.

公开(公告)号：US12009395B2

公开(公告)日：2024-06-11

申请号：US17404014

申请日：2021-08-17

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Junli Wang ,  Choonghyun Lee ,  Alexander Reznicek

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/41741 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/7827 ,  H01L29/785

Abstract: A vertical FET includes a channel fin between a bottom source/drain (S/D) region and a top S/D region, a gate upon a sidewall of the channel fin, a top metallization upon the top S/D region, a first contact metallization connected to the gate, a second contact metallization connected to the bottom S/D region, a first vertical liner between a portion of the gate and the first contact metallization, and a second vertical liner between the top metallization and the second contact metallization. The vertical FET may be fabricated by forming a self-aligned block and utilizing the self-aligned block to e.g., prevent gate to gate shorting during replacement gate formation or processing.

公开(公告)号：US11996480B2

公开(公告)日：2024-05-28

申请号：US17470686

申请日：2021-09-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki ,  Choonghyun Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41741 ,  H01L29/66666

Abstract: VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.

公开(公告)号：US11756960B2

公开(公告)日：2023-09-12

申请号：US17483981

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  Takashi Ando ,  Choonghyun Lee

IPC: H01L27/092 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/3115 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/0673 ,  H01L29/408 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/78618 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A method for forming a semiconductor device structure includes removing a portion of a first dielectric layer surrounding each of a plurality of channel layers of at least a first nanosheet stack. A portion of a second dielectric layer surrounding each of a plurality of channel layers of at least a second nanosheet stack is crystallized. A dipole layer is formed on the etched first dielectric layer and the crystallized portion of the second dielectric layer. The dipole layer is diffused into the etched first dielectric layer. The crystallized portion of the second dielectric layer prevents the dipole layer form diffusing into the second dielectric layer.

公开(公告)号：US20230072305A1

公开(公告)日：2023-03-09

申请号：US17470686

申请日：2021-09-09

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Shogo Mochizuki ,  Choonghyun Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66

Abstract: VFET devices having symmetric, sharp channel-to-source/drain junctions and techniques for fabrication thereof using a late source/drain epitaxy process are provided. In one aspect, a VFET device includes: at least one vertical fin channel disposed on a substrate; a gate stack alongside the at least one vertical fin channel; a bottom source/drain region directly below the at least one vertical fin channel having, for example, an inverted T-shape with a flat bottom; and a top source/drain region over the at least one vertical fin channel. A method of fabricating a VFET device is also provided.

公开(公告)号：US20230055297A1

公开(公告)日：2023-02-23

申请号：US17404014

申请日：2021-08-17

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Junli Wang ,  Choonghyun Lee ,  Alexander Reznicek

IPC: H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06

Abstract: A vertical FET includes a channel fin between a bottom source/drain (S/D) region and a top S/D region, a gate upon a sidewall of the channel fin, a top metallization upon the top S/D region, a first contact metallization connected to the gate, a second contact metallization connected to the bottom S/D region, a first vertical liner between a portion of the gate and the first contact metallization, and a second vertical liner between the top metallization and the second contact metallization. The vertical FET may be fabricated by forming a self-aligned block and utilizing the self-aligned block to e.g., prevent gate to gate shorting during replacement gate formation or processing.

公开(公告)号：US11527616B2

公开(公告)日：2022-12-13

申请号：US16953447

申请日：2020-11-20

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Choonghyun Lee ,  Jingyun Zhang ,  Alexander Reznicek

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/51

Abstract: A semiconductor structure for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including the SiGe layer and a second material layer formed on the SiGe layer, a first high-κ metal gate disposed over the first set of fins, and a second high-κ metal gate disposed over the second set of fins. An asymmetric threshold voltage is present along the channel of the VTFET in a region defined at a bottom of the first and second set of fins, and a Ge content of the second material layer is higher than a Ge content of the SiGe layer.