公开(公告)号：US20150129955A1

公开(公告)日：2015-05-14

申请号：US14075480

申请日：2013-11-08

Applicant: Micron Technology, Inc.

Inventor： Wolfgang Mueller ,  Sanh D. Tang ,  Sourabh Dhir ,  Srinivas Pulugurtha

IPC: H01L29/78 ,  H01L27/105 ,  H01L29/66

CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

Abstract: A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed.

Abstract translation: 半导体器件可以包括存储器阵列，其包括连接到数字线，字线和主体连接线的垂直存储器单元。 存储器阵列的行或列可以包括连接到主体连接线的一个或多个支柱。 可以通过连接到主体连接线的至少一个支柱将电压施加到主体连接线。 施加电压到身体连接线可能会减少浮体效应。 公开了形成至少一个柱和电压源之间的连接的方法。 还公开了包括这种连接的半导体器件。

公开(公告)号：US20150069482A1

公开(公告)日：2015-03-12

申请号：US14024347

申请日：2013-09-11

Applicant: Micron Technology, Inc.

Inventor： Wolfgang Mueller ,  Sanh D. Tang

IPC: H01L27/108 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/0207 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/78

Abstract: Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first direction. Cell active material structures are at intersections of the wordlines and bitlines. The cell active material structures have a first side coupled to a bitline and a second side coupled to a capacitor. The second side is on an opposite side of a wordline passing through a cell active material structure relative to the first side. Each cell active material structure has a connection to a bitline which is not shared with any other cell active material structures. Some embodiments include DRAM arrays and semiconductor constructions.

Abstract translation: 一些实施例包括DRAM阵列布局。 字线沿着第一方向延伸，并且位线沿着穿过第一方向的第二方向延伸。 电池活性材料结构在字线和位线的交点处。 电池活性材料结构具有耦合到位线的第一侧和耦合到电容器的第二侧。 第二面位于相对于第一侧穿过细胞活性材料结构的字线的相反侧。 每个电池活性材料结构具有与不与任何其它电池活性材料结构共享的位线的连接。 一些实施例包括DRAM阵列和半导体结构。

公开(公告)号：US20150028406A1

公开(公告)日：2015-01-29

申请号：US13948746

申请日：2013-07-23

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L29/423 ,  H01L29/06 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L21/76232 ,  H01L23/528 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Abstract translation: 一组凹进的存取栅极线包括其间具有介电沟槽隔离材料的有源区域区域。 沟槽隔离材料包括延伸到有源区域区域的材料的最外表面下方的各个有源区域的相对端的电介质突起。 有源区域材料在电介质突起上是垂直的。 嵌入式栅极线分别横跨有源区域区域延伸并且在电介质沟槽隔离材料内的紧邻端到端相邻有源区域区域的端部之间延伸。 公开了其他阵列，方法也是如此。

公开(公告)号：US20140339494A1

公开(公告)日：2014-11-20

申请号：US14448352

申请日：2014-07-31

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

IPC: H01L45/00

CPC classification number: H01L45/1226 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

Abstract: Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

Abstract translation: 一些实施例包括存储器单元。 存储单元可以具有第一电极和在第一电极上方的沟槽状可编程材料结构。 沟槽形状限定开口。 可编程材料可以被配置为可逆地保持导电桥。 存储单元可以具有直接抵靠可编程材料的离子源材料，并且可以在由沟槽状可编程材料限定的开口内具有第二电极。 一些实施例包括存储器单元阵列。 阵列可以具有第一导电线，以及在第一线上的沟槽状可编程材料结构。 沟槽状结构可以在其内限定开口。 离子源材料可以直接抵靠可编程材料，并且第二导电线可以在离子源材料之上并且在由沟槽状结构限定的开口内。

公开(公告)号：US08859359B2

公开(公告)日：2014-10-14

申请号：US13953450

申请日：2013-07-29

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak ,  Werner Juengling

IPC: H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L29/423 ,  H01L27/12 ,  H01L27/108

CPC classification number: H01L27/10802 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/7841

Abstract: Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.

公开(公告)号：US20140302650A1

公开(公告)日：2014-10-09

申请号：US14310790

申请日：2014-06-20

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L29/792

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

Abstract translation: 描述形成多层半导体器件的方法以及包括它们的装置和系统。 在一种这样的方法中，在半导体材料层和电介质层中形成开口。 通过开口暴露的半导体材料层的一部分被处理，使得该部分与该层中剩余的半导体材料不同地掺杂。 至少基本上所有剩余的层的半导体材料被去除，留下半导体材料层的不同掺杂部分作为电荷存储结构。 在电荷存储结构的第一表面上形成隧道电介质，并且在电荷存储结构的第二表面上形成隔间电介质。 还描述了另外的实施例。

公开(公告)号：US08841715B2

公开(公告)日：2014-09-23

申请号：US13952742

申请日：2013-07-29

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak ,  Werner Juengling

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L27/12 ,  H01L29/78 ,  H01L29/423 ,  H01L21/84

CPC classification number: H01L27/10802 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/7841

Abstract: Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.

Abstract translation: 包括浮置体细胞结构，其包括布置在背栅上的浮体阵列阵列和与后门间隔开的浮体细胞的源区和漏区。 浮体细胞可以各自包括体积的半导体材料，其具有在柱之间延伸的通道区域，其可以通过诸如U形沟槽的空隙分开。 阵列的浮体电池可以电耦合到另一个栅极，另一个栅极可以设置在半导体材料的体积的侧壁上或其内的空隙中。 还公开了形成浮体电池器件的方法。

公开(公告)号：US20140151776A1

公开(公告)日：2014-06-05

申请号：US14090689

申请日：2013-11-26

Applicant: Micron Technology, Inc.

Inventor： Kurt D. Beigel ,  Sanh D. Tang

IPC: H01L29/06 ,  H01L29/788

CPC classification number: H01L29/0638 ,  H01L27/1027 ,  H01L27/10802 ,  H01L29/0688 ,  H01L29/7841 ,  H01L29/78642 ,  H01L29/7889

Abstract: Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.

Abstract translation: 提供了形成装置的方法以及与垂直存储单元相关联的装置。 形成垂直存储单元的一个示例性方法可以包括在导体线上形成半导体结构。 半导体结构可以具有包括第一和第二掺杂材料之间的第一结的第一区域。 在第一区域上方的半导体结构的第一对侧壁上形成蚀刻保护材料。 第一区域的体积相对于半导体结构的体区在第一维度上减小。

公开(公告)号：US08659075B2

公开(公告)日：2014-02-25

申请号：US13751902

申请日：2013-01-28

Applicant: Micron Technology, Inc.

Inventor： John Zahurak ,  Sanh D. Tang ,  Gurtej S. Sandhu

IPC: H01L29/66

CPC classification number: H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/105 ,  H01L27/24 ,  H01L29/66666 ,  H01L29/7827

Abstract: Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.

Abstract translation: 形成具有支柱的存储器单元阵列和存储单元阵列的方法。 单个柱可以具有由半导体柱上的体半导体材料和牺牲帽形成的半导体柱。 源区可以在柱的列之间，并且栅极线沿着柱柱延伸并且与相应的源极区域间隔开。 每个栅极线沿着一列柱围绕半导体柱的一部分。 可以选择性地去除牺牲帽结构，从而形成露出相应半导体柱的顶部的自对准开口。 形成在自对准开口中的单独的漏极触点电连接到相应的半导体柱。

公开(公告)号：US20140015001A1

公开(公告)日：2014-01-16

申请号：US14028242

申请日：2013-09-16

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak ,  Michael P. Violette

IPC: H01L29/74

CPC classification number: H01L29/66363 ,  H01L27/1027 ,  H01L29/42308 ,  H01L29/74 ,  H01L2924/1301

Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.

Abstract translation: 显示存储器件和制造存储器件的方法。 所示的方法和配置提供用于增加存储器密度的折叠和垂直存储器件。 提供的方法减少了对诸如深掺杂剂植入物的制造方法的需要。