公开(公告)号：US08771537B2

公开(公告)日：2014-07-08

申请号：US13391196

申请日：2010-08-10

申请人： Toshihisa Ozu ,  Naoki Matsumoto ,  Takashi Tsukamoto ,  Kazuto Takai

发明人： Toshihisa Ozu ,  Naoki Matsumoto ,  Takashi Tsukamoto ,  Kazuto Takai

IPC分类号： B44C1/22

CPC分类号： H01L21/67069 ,  H01J37/3244 ,  H01J37/32449 ,  H01L21/31116 ,  H01L21/32137

摘要： Uniformity of a plasma process on a surface of a substrate is to be improved. In a plasma processing apparatus that processes a substrate by generating plasma from a processing gas introduced in a processing container, a ratio between an introducing amount of the processing gas introduced to a center portion of the substrate received in the processing container and an introducing amount of the processing gas introduced to a peripheral portion of the substrate received in the processing container is changed during a plasma process. Accordingly, a variation in an etching rate or the like between the center portion and the peripheral portion of the substrate may be reduced. Therefore, uniformity of the plasma process on the surface of the substrate is improved.

摘要翻译： 改善基板表面上的等离子体工艺的均匀性。 在通过从处理容器中导入的处理气体产生等离子体来处理基板的等离子体处理装置中，导入到处理容器内的基板的中心部分的加工气体的导入量与导入量 在等离子体处理中改变了被引入处理容器内的基板周边部分的处理气体。 因此，可以减小衬底的中心部分和周边部分之间的蚀刻速率等的变化。 因此，提高了衬底表面上的等离子体处理的均匀性。

公开(公告)号：US08404569B2

公开(公告)日：2013-03-26

申请号：US12949268

申请日：2010-11-18

申请人： Hitoshi Kasai ,  Takuji Okahisa ,  Shunsuke Fujita ,  Naoki Matsumoto ,  Hideyuki Ijiri ,  Fumitaka Sato ,  Kensaku Motoki ,  Seiji Nakahata ,  Koji Uematsu ,  Ryu Hirota

发明人： Hitoshi Kasai ,  Takuji Okahisa ,  Shunsuke Fujita ,  Naoki Matsumoto ,  Hideyuki Ijiri ,  Fumitaka Sato ,  Kensaku Motoki ,  Seiji Nakahata ,  Koji Uematsu ,  Ryu Hirota

IPC分类号： H01L21/00

CPC分类号： H01L21/02617 ,  C23C16/303 ,  C23C16/4405 ,  C23C16/4488 ,  C30B23/02 ,  C30B25/02 ,  C30B29/403

摘要： A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.

公开(公告)号：US20130032013A1

公开(公告)日：2013-02-07

申请号：US13535606

申请日：2012-06-28

申请人： Hidenori MIKAMI ,  Naoki Matsumoto

发明人： Hidenori MIKAMI ,  Naoki Matsumoto

IPC分类号： B26D1/00

CPC分类号： B28D5/045 ,  B23D61/185 ,  C30B29/403 ,  C30B33/00 ,  C30B33/06 ,  Y10T83/04

摘要： A method of manufacturing a group III nitride crystal substrate includes the step of preparing a group III nitride crystal body and the step of producing a group III nitride crystal substrate by slicing the group III nitride crystal body with a resin-fixed-abrasive wire. Accordingly, the method of manufacturing a group III nitride crystal substrate is provided that enables large-sized group III nitride crystal substrates with a small warp and a small arithmetic mean surface roughness to be manufactured by means of a resin-fixed-abrasive wire efficiently with a high yield.

摘要翻译： 制造III族氮化物晶体衬底的方法包括制备III族氮化物晶体的步骤和通过用树脂固定研磨线切割III族氮化物晶体来制备III族氮化物晶体衬底的步骤。 因此，提供了制造III族氮化物晶体基板的方法，其能够通过树脂固定磨料线有效地制造具有小经纱和小算术平均表面粗糙度的大尺寸III族氮化物晶体基板， 高产量。

公开(公告)号：US08368366B2

公开(公告)日：2013-02-05

申请号：US12553755

申请日：2009-09-03

申请人： Yuji Kuwana ,  Naoki Matsumoto ,  Yasuhiro Urabe

发明人： Yuji Kuwana ,  Naoki Matsumoto ,  Yasuhiro Urabe

IPC分类号： G05F1/40

CPC分类号： H03F3/45

摘要： Provided is a driver circuit that outputs, from an output end, an output signal corresponding to an input signal supplied thereto, comprising an output resistance section that is provided between a constant voltage source and the output end; an output switching section that switches voltage of the output end according to the input signal; and a switching section that switches a resistance value of the output resistance section. The output resistance section includes an output resistance FET having a source/drain connection between the constant voltage source and the output end, and the switching section supplies a control voltage to a gate of the output resistance FET such that the resistance between the source and the drain of the output resistance FET switches to a designated value.

摘要翻译： 提供了一种从输出端输出与提供给其的输入信号相对应的输出信号的驱动器电路，包括设置在恒定电压源和输出端之间的输出电阻部分; 输出切换部，其根据输入信号切换输出端的电压; 以及切换部，切换输出电阻部的电阻值。 输出电阻部分包括在恒定电压源和输出端之间具有源极/漏极连接的输出电阻FET，并且开关部分向输出电阻FET的栅极提供控制电压，使得源极和源极之间的电阻 输出电阻FET的漏极切换到指定值。

公开(公告)号：US20120135549A1

公开(公告)日：2012-05-31

申请号：US13366386

申请日：2012-02-06

申请人： Masahiro Nakayama ,  Naoki Matsumoto

发明人： Masahiro Nakayama ,  Naoki Matsumoto

IPC分类号： H01L21/66

CPC分类号： H01L21/02019 ,  H01L21/30612

摘要： Polishing a nitride semiconductor monocrystalline wafer leaves it with a process-transformed layer. The process-transformed layer has to be etched to be removed. The chemical inertness of nitride semiconductor materials has, however, precluded suitable etching. Although potassium hydroxide, for example, or sulfuric acid have been proposed as GaN etchants, their ability to corrosively remove material from the Ga face is weak. Dry etching utilizing a halogen plasma is carried out in order to remove the process-transformed layer. The Ga face can be etched off with the halogen plasma. Nevertheless, owing to the dry etching, a problem arises again—surface contamination due to metal particles. To address the problem, wet etching with, as the etchant, solutions such as HF+H2O2, H2SO4+H2O2, HCl+H2O2, or HNO3, which are nonselective for Ga/N faces, have metal etching capability, and have an oxidation-reduction potential of 1.2 V or more, is performed.

摘要翻译： 抛光氮化物半导体单晶晶片使其具有工艺转换层。 工艺转换层必须被蚀刻以去除。 然而，氮化物半导体材料的化学惰性已经排除了适当的蚀刻。 尽管已经提出了例如氢氧化钾或硫酸作为GaN蚀刻剂，但是它们从Ga面腐蚀性去除材料的能力较弱。 进行使用卤素等离子体的干法蚀刻以去除工艺转变层。 Ga面可以用卤素等离子体蚀刻掉。 然而，由于干蚀刻，再次出现了由金属颗粒引起的表面污染。 为了解决这个问题，作为蚀刻剂，对于Ga / N面非选择性的HF + H 2 O 2，H 2 SO 4 + H 2 O 2，HCl + H 2 O 2或HNO 3等溶液进行湿式蚀刻，具有金属蚀刻能力， 还原电位为1.2V以上。

公开(公告)号：USD645486S1

公开(公告)日：2011-09-20

申请号：US29369644

申请日：2010-09-10

申请人： Wataru Yoshikawa ,  Naoki Matsumoto ,  Jun Yoshikawa

设计人： Wataru Yoshikawa ,  Naoki Matsumoto ,  Jun Yoshikawa

公开(公告)号：US20110195155A1

公开(公告)日：2011-08-11

申请号：US13124510

申请日：2009-10-02

申请人： Megumi Nakagawa ,  Naoki Matsumoto ,  Hitoshi Amano ,  Shotaro Yamaguchi

发明人： Megumi Nakagawa ,  Naoki Matsumoto ,  Hitoshi Amano ,  Shotaro Yamaguchi

IPC分类号： C12N15/80 ,  C12N9/18 ,  C12N1/15 ,  C07H21/04 ,  A23L2/00

CPC分类号： C12N9/18 ,  C12P7/42

摘要： Disclosed is a thermostable tannase derived from a microorganism. Specifically disclosed is a thermostable tannase derived from Aspergillus awamori or Aspergillus niger. A preferred embodiment of the tannase has the following chemoenzymatic properties: (1) activity: to act on a depside bond to thereby cause hydrolysis; (2) molecular weight: about 230,000 Da (as measured by gel filtration); and (3) thermal stability: stable at a temperature up to 65° C. (pH 5.0, 30 min.)

摘要翻译： 公开了一种衍生自微生物的热稳定性鞣酸酶。 具体公开了源自泡盛曲霉或黑曲霉的热稳定性鞣酸酶。 鞣酸酶的优选实施方案具有以下化学酶学性质：（1）活性：作用于脱附键从而引起水解; （2）分子量：约230,000Da（通过凝胶过滤测量）; 和（3）热稳定性：在高达65℃的温度下稳定（pH5.0,30分钟）

公开(公告)号：US20100109788A1

公开(公告)日：2010-05-06

申请号：US12584456

申请日：2009-09-04

申请人： Naoki Matsumoto ,  Takashi Sekino ,  Takayuki Nakamura

发明人： Naoki Matsumoto ,  Takashi Sekino ,  Takayuki Nakamura

IPC分类号： H03C3/00 ,  G06G7/14 ,  G06G7/19

CPC分类号： H03K19/01806 ,  G01R31/318357 ,  H04B3/144 ,  H04B3/40 ,  H04L25/0286

摘要： In a driver circuit 10 for outputting a simulated signal simulating an input signal subjected to transmission loss, corresponding to the input signal, the driver circuit 10 comprises: a main driver 18 which receives the input signal and outputs an output signal corresponding to the input signal; a sub driver 20 which receives the input signal and outputs an output signal given by inverting the input signal; a high frequency emphasizing circuit 22 which receives the input signal of the sub driver 20 and outputs an output signal having the high frequency of the input signal of the sub driver 20 emphasized; and an addition unit 24 which outputs the simulated signal given by adding the output signal of the main driver 18 and the output signal of the high frequency emphasizing circuit 22.

摘要翻译： 在驱动电路10中，驱动电路10输出与模拟输入信号相对应的输入信号的仿真信号，驱动电路10包括：主驱动器18，其接收输入信号并输出​​与输入信号对应的输出信号 ; 子驱动器20，其接收输入信号并输出​​通过反相输入信号给出的输出信号; 接收子驱动器20的输入信号并输出​​具有副驱动器20的输入信号的高频的输出信号的高频加重电路22; 以及加法单元24，其输出通过将主驱动器18的输出信号和高频加重电路22的输出信号相加而给出的模拟信号。

公开(公告)号：US07679390B2

公开(公告)日：2010-03-16

申请号：US12138442

申请日：2008-06-13

申请人： Naoki Matsumoto ,  Takashi Sekino

发明人： Naoki Matsumoto ,  Takashi Sekino

IPC分类号： G01R31/02

CPC分类号： G01R31/31924 ,  G01R31/3191

摘要： Provided is a test apparatus that tests a DUT, which includes a driver that outputs a test signal to the DUT, a first transmission path that electrically connects the driver and the DUT, a first FET switch provided on the first transmission path to connect or disconnect the driver and the DUT to or from each other, and a capacitance compensator that detects an output signal from the DUT, and charges or discharges a capacitive component of the first FET switch based on the detected output signal.

摘要翻译： 提供了一种测试DUT，其包括向DUT发送测试信号的驱动器，电连接驱动器和DUT的第一传输路径，设置在第一传输路径上以连接或断开的第一FET开关 所述驱动器和所述DUT彼此相互连接，以及电容补偿器，其检测来自所述DUT的输出信号，并且基于所检测的输出信号对所述第一FET开关的电容分量进行充电或放电。

公开(公告)号：US20090263955A1

公开(公告)日：2009-10-22

申请号：US12382180

申请日：2009-03-10

申请人： Kensaku Motoki ,  Takuji Okahisa ,  Naoki Matsumoto

发明人： Kensaku Motoki ,  Takuji Okahisa ,  Naoki Matsumoto

IPC分类号： H01L21/20 ,  H01L21/304

CPC分类号： C30B25/02 ,  B82Y20/00 ,  C30B25/00 ,  C30B29/406 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L33/007 ,  H01L33/0075 ,  H01S5/0206 ,  H01S5/34333 ,  H01S2304/00 ,  H01S2304/04 ,  Y10S117/902 ,  Y10S438/942

摘要： The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.