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    Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate
    191.
    发明申请
    Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate 有权
    使用绝缘体上硅衬底制造嵌入式存储器件的方法

    公开(公告)号：US20160086962A1

    公开(公告)日：2016-03-24

    申请号：US14491596

    申请日：2014-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do ,  Jeng-Wei Yang

    IPC: H01L27/115 ,  H01L21/762 ,  H01L29/423 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06

    CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/7624 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825

    Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

    Abstract translation: 形成半导体器件的方法从硅衬底，硅上的第一绝缘层和第一绝缘层上的硅层开始。 仅从第二衬底区域去除硅层和绝缘层。 第二绝缘层形成在衬底第一区域中的硅层之上并且在第二衬底区域中的硅上方。 第一多个沟槽形成在第一衬底区域中，每个沟槽延伸穿过所有层并进入硅中。 第二多个沟槽形成在第二衬底区域中，每个沟槽延伸穿过第二绝缘层并进入硅中。 绝缘材料形成在第一和第二沟槽中。 逻辑器件形成在第一衬底区域中，并且存储器单元形成在第二衬底区域中。

    Non-volatile Memory Device And A Method Of Programming Such Device
    193.
    发明申请
    Non-volatile Memory Device And A Method Of Programming Such Device 有权
    非易失性存储器件及其编程方法

    公开(公告)号：US20150003166A1

    公开(公告)日：2015-01-01

    申请号：US14449926

    申请日：2014-08-01

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

    IPC: G11C16/10 ,  G11C16/26 ,  H01L27/115

    CPC classification number: G11C16/10 ,  G11C7/00 ,  G11C7/22 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/2263 ,  G11C2211/5647 ,  H01L27/11517

    Abstract: A non-volatile memory device has a charge pump for providing a programming current and an array of non-volatile memory cells. Each memory cell of the array is programmed by the programming current from the charge pump. The array of non-volatile memory cells is partitioned into a plurality of units, with each unit comprising a plurality of memory cells. An indicator memory cell is associated with each unit of non-volatile memory cells. A programming circuit programs the memory cells of each unit using the programming current, when fifty percent or less of the memory cells of each unit is to be programmed, and programs the inverse of the memory cells of each unit and the indicator memory cell associated with each unit, using the programming current, when more than fifty percent of the memory cells of each unit is to be programmed.

    Abstract translation: 非易失性存储器件具有用于提供编程电流和非易失性存储器单元阵列的电荷泵。 阵列的每个存储单元都由来自电荷泵的编程电流编程。 非易失性存储器单元的阵列被分割成多个单元，每个单元包括多个存储器单元。 指示器存储单元与每单位的非易失性存储单元相关联。 编程电路使用编程电流来对每个单元的存储器单元进行编程，当每个单元的存储单元的百分之五十或更少被编程时，编程每个单元的存储器单元的反相和与 每个单元使用编程电流时，每个单元的存储单元的百分之五十以上将被编程。

    INPUT BLOCK FOR VECTOR-BY-MATRIX MULTIPLICATION ARRAY
    196.
    发明申请
    INPUT BLOCK FOR VECTOR-BY-MATRIX MULTIPLICATION ARRAY 有权

    公开(公告)号：US20250068861A1

    公开(公告)日：2025-02-27

    申请号：US18385344

    申请日：2023-10-30

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Stephen Trinh ,  Hoa Vu ,  Stanley Hong ,  Thuan Vu

    IPC: G06J1/00

    Abstract: Numerous examples are disclosed of input blocks for an array of non-volatile memory cells and associated methods. In one example, a system comprises a vector-by-matrix multiplication array comprising non-volatile memory cells arranged into rows and columns; and an input block comprising a plurality of row circuits and a global digital-to-analog converter generator to generate 2m different analog voltages, where m is an integer; wherein the row circuits in the plurality of row circuits respectively apply one of the 2m different analog voltages to an associated row in the array.

    ROW DECODER AND ROW ADDRESS SCHEME IN A MEMORY SYSTEM
    199.
    发明公开
    ROW DECODER AND ROW ADDRESS SCHEME IN A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240339136A1

    公开(公告)日：2024-10-10

    申请号：US18206488

    申请日：2023-06-06

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Kha Nguyen ,  Anh Ly ,  Hieu Van Tran ,  Hien Pham ,  Henry Tran

    IPC: G11C7/10 ,  G11C7/12

    CPC classification number: G11C7/1039 ,  G11C7/12

    Abstract: Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m≤2u, n≤2v, and p≤2t.

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