公开(公告)号：US09018057B1

公开(公告)日：2015-04-28

申请号：US14048263

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Nicolas Loubet

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L29/49 ,  H01L29/165 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02532 ,  H01L21/2251 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/7848

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

Abstract translation: 一种用于形成互补金属氧化物半导体（CMOS）半导体器件的方法包括提供包括具有第一和第二横向相邻应力半导体部分的应力半导体层的受应力的绝缘体上硅（sSOI）晶片。 第一应力半导体部分限定第一有源区。 第二应力半导体部分被未受应力的半导体部分代替。 未受应力的半导体部分包括第一半导体材料。 该方法还包括将第二半导体材料驱动到限定第二有源区的无应力半导体部分的第一半导体材料中。

公开(公告)号：US08975168B2

公开(公告)日：2015-03-10

申请号：US13903630

申请日：2013-05-28

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Nicolas Loubet

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/00 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/823821 ,  H01L21/845

Abstract: A SOI substrate layer formed of a silicon semiconductor material includes adjacent first and second regions. A portion of the silicon substrate layer in the second region is removed such that the second region retains a bottom portion made of the silicon semiconductor material. An epitaxial growth of a silicon-germanium semiconductor material is made to cover the bottom portion. Germanium is then driven from the epitaxially grown silicon-germanium material into the bottom portion to convert the bottom portion to silicon-germanium. Further silicon-germanium growth is performed to define a silicon-germanium region in the second region adjacent the silicon region in the first region. The silicon region is patterned to define a first fin structure of a FinFET of a first (for example, n-channel) conductivity type. The silicon-germanium region is also patterned to define a second fin structure of a FinFET of a second (for example, p-channel) conductivity type.

Abstract translation: 由硅半导体材料形成的SOI衬底层包括相邻的第一和第二区域。 去除第二区域中的硅衬底层的一部分，使得第二区域保持由硅半导体材料制成的底部。 制造硅 - 锗半导体材料的外延生长以覆盖底部。 然后将锗从外延生长的硅 - 锗材料驱动到底部，以将底部部​​分转化为硅 - 锗。 执行进一步的硅 - 锗生长以在与第一区域中的硅区域相邻的第二区域中限定硅 - 锗区域。 图案化硅区域以限定第一（例如，n沟道）导电类型的FinFET的第一鳍结构。 硅 - 锗区域也被图案化以限定第二（例如p沟道）导电类型的FinFET的第二鳍结构。

公开(公告)号：US20140299880A1

公开(公告)日：2014-10-09

申请号：US14309409

申请日：2014-06-19

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

IPC: H01L29/10 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/1033 ,  H01L29/04 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78

Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

Abstract translation: 可以在半导体器件区域上形成绝缘层，并以基本上减少或防止下面的沟道区域的蚀刻量的方式进行蚀刻。 可以在栅极区域和半导体器件区域上形成第一绝缘层。 可以在第一绝缘层上形成第二绝缘层。 可以在第二绝缘层上形成第三绝缘层。 可以使用第一蚀刻工艺蚀刻第三绝缘层的一部分。 可以使用与第一蚀刻工艺不同的至少第二蚀刻工艺来蚀刻第三绝缘层的蚀刻部分下方的第一绝缘层和第二绝缘层的一部分。

公开(公告)号：US20140151759A1

公开(公告)日：2014-06-05

申请号：US13692632

申请日：2012-12-03

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/20 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/06 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.

Abstract translation: 在外延生长的晶体中存在小面或空隙，表明晶体生长已被缺陷或某些材料边界中断。 在形成应变硅晶体管的源极和漏极区域的硅化合物的外延生长期间，可以抑制刻面。 已经观察到，当某些硅化合物的外延层相邻于氧化物边界生长时，可以发生刻面，但是当外延层生长在邻近硅边界或与氮化物边界相邻时，不会发生刻面。 因为硅化合物的外延生长通常在填充有氧化物的隔离沟槽附近是必要的，所以在这些区域中抑制刻面的技术是特别有意义的。 本文提出的一种这样的技术是使隔离沟槽与SiN对准，以在氧化物和预期外延生长的区域之间提供阻挡层。

公开(公告)号：US10943837B2

公开(公告)日：2021-03-09

申请号：US16399808

申请日：2019-04-30

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L29/161 ,  H01L29/423 ,  H01L21/84 ,  H01L21/266 ,  H01L21/265 ,  H01L21/308 ,  H01L29/66

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US10340195B2

公开(公告)日：2019-07-02

申请号：US15813071

申请日：2017-11-14

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/308

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

公开(公告)号：US20180350808A1

公开(公告)日：2018-12-06

申请号：US16049685

申请日：2018-07-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L27/088 ,  H01L21/225 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US20180301547A1

公开(公告)日：2018-10-18

申请号：US16013095

申请日：2018-06-20

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Salih Muhsin Celik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/51 ,  H01L29/739

CPC classification number: H01L29/66977 ,  H01L29/0649 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/165 ,  H01L29/4941 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/7851

Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

公开(公告)号：US10043907B2

公开(公告)日：2018-08-07

申请号：US15162441

申请日：2016-05-23

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L29/49 ,  H01L29/165 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L21/225 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

公开(公告)号：US20180158739A1

公开(公告)日：2018-06-07

申请号：US15890001

申请日：2018-02-06

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L27/12 ,  H01L27/02 ,  H01L21/308 ,  H01L21/266

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3081 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/66795

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.