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    THREE-DIMENSIONAL MEMORY APPARATUS AND METHOD OF MANUFACTURING THE SAME
    205.
    发明申请
    THREE-DIMENSIONAL MEMORY APPARATUS AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20180138241A1

    公开(公告)日：2018-05-17

    申请号：US15855958

    申请日：2017-12-27

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: A three dimensional (3D) memory array and method of manufacturing the same are described. The 3D memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. A memory cell included in the memory material is aligned in a same plane as the electrode plane, and the memory cell is configured to exhibit a first threshold voltage representative of a first logic state and a second threshold voltage representative of a second logic state. A conductive pillar is disposed through and coupled to the memory cell, wherein the conductive pillar and electrode plane are configured to provide a voltage across the memory cell to write a logic state to the memory cell. Methods to operate and to form the 3D memory array are disclosed.

    Array Of Cross Point Memory Cells And Methods Of Forming An Array Of Cross Point Memory Cells
    206.
    发明申请
    Array Of Cross Point Memory Cells And Methods Of Forming An Array Of Cross Point Memory Cells 审中-公开

    公开(公告)号：US20180138239A1

    公开(公告)日：2018-05-17

    申请号：US15851112

    申请日：2017-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Stephen W. Russell ,  Tony M. Lindenberg

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.

    Methods of forming memory arrays
    208.
    发明授权
    Methods of forming memory arrays 有权

    公开(公告)号：US09917253B2

    公开(公告)日：2018-03-13

    申请号：US15596397

    申请日：2017-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1675 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666

    Abstract: Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.

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